February 1995 v.46 n.1

Cover: This high-speed fiber-optic polarimeter is used in the HP 8509B polarization analyzer, an instrument that can characterize polarization-mode dispersion problems in long fiber systems.

Broadband Frequency Characterization of Optical Receivers Using Intensity Noise. Methods for enhancing the dynamic range of the intensity noise technique for high-frequency photoreceiver calibration are proposed and experimentally demonstrated. These methods combine recently developed EDFA technology with spectral filtering techniques. The intensity noise calibration technique is portable, easy to use, and field deployable, by Wayne V. Sorin, Douglas M. Baney, pg 6-12

1.55-mm Fiber-Optic Amplifier, pg 9

Erbium-Doped Fiber Amplifier Test System. The HP 81600 Series 200 EDFA test system combines various instruments with powerful software to characterize erbium-doped fiber amplifiers. The system is a turnkey solution with fully specified uncertainty, by Christian Hentschel, Clemens Ruck, Edgar Leckel, Jurgen Sang, Rolf Muller, pg 13-19

Multi-Quantum-Well Ridge Waveguide Lasers for Tunable External-Cavity Sources. A new multi-quantum-well ridge waveguide laser enhanced for use in a grating-tuned external-cavity source has been developed. The device offers higher output power and wider tunability for improved performance in a new instrument. A core technology has been developed for use in a variety of light-emitting devices, by William H. Perez, David M. Braun, Michael J. Ludowise, Tim L. Bagwell, Tirumala R. Ranganath, Dennis J. Derickson, Patricia A. Beck, pg 20-26

Measurement of Polarization-Mode Dispersion. Polarization-mode dispersion is defined and characterized, using Poincare sphere and Jones matrix concepts. Interferometric, wavelength scanning, and Jones matrix eigenanalysis measurement methods are described. Instrumentation, especially the HP 8509B lightwave polarization analyzer, is discussed, by Paul R. Hernday, Brian L. Heffner, pg 27-33

Jones Calculus, pg 28

The Poincare Sphere, pg 29

The HP 8509A/B Lightwave Polarization Analyzer, pg 32

A New Design Approach for a Programmable Optical Attenuator. The new HP 8156A optical attenuator offers improved performance, low polarization dependent loss and polarization-mode dispersion, and increased versatility. It uses a birefrignence-free glass filter disk and a high-resolution, fast-settling filter driver system, by Halmo Fischer, Siegmar Schmidt, pg 34-39

Precision Reflectometer with Spurious-Free Enhanced Sensitivity. The HP 8504B precision reflectrometer has an improved sensitivity of -80 dB at both 1300-nm and 1550-nm wavelengths. All spurious responses generated within the instrument itself have been significantly reduced. The instrument offers fiber-optic component designers and manufacturers the ability to pinpoint both large and small optical reflectances, by Luis M. Fernandez, David M. Braun, Greg D. LeCheminant, Dennis J. Derickson, pg 39-42

High-Power, Low-Internal-Reflection, Edge Emitting Light-Emitting Diodes. A new edge emitting LED has been developed for applications in optical low-coherence reflectrometry. It offers improved sensitivity without introducing spurious responses, by Julie E. Fouquet, Tim L. Bagwell, David M. Braun, Patricia A. Beck, Susan R. Sloan, Dennis J. Derickson, William H. Perez, Gary R. Trott, Forrest G. Kellert, Tirumala R. Ranganath, Michael J. Ludowise, pg 43-48. LEDs, EELED, 8504B.

Jitter Analysis of High-Speed Digital Systems. The HP 71501B jitter and eye diagram analyzer performs industry-standard jitter tolerance, jitter transfer, and jitter generation measurements on Gbit/s telecommunication system components. It can display both the jitter spectrum and the jitter waveform to help determine whether jitter is limiting the bit error ratio of a transmission system, by Christopher M. Miller, David J. McQuate, pg 49-56

Automation of Optical Time-Domain Reflectometry Measurements. The HP 81700 Series 100 remote fiber test system is a first-generation system consisting of a personal computer controlling one or more OTDRs and optical switches. It is well-suited for automated testing of small fiber networks such as company networks, by Harald Seeger, Frank A. Maier, pg 57-62

Design and Performance of a Narrowband VCO at 282 THz. A single-mode optical signal source whose frequency can be voltage-controlled has been developed. We describe its design and performance, by Peter R. Robrish, Rory L.VanTuyl, Christopher J. Madden, William R. Trutna, Jr., pg 63-66

Surface Emitting Laser for Multimode Data Link Applications. A surface emitting laser has been developed for use in a multimode optical fiber data link. The laser can operate in a high-order spatial mode, resulting in a spectral width as wide as one nanometer and a relative intensity noise (RIN) lower than -125 dB/Hz in a multimode fiber system. Electrical and optical characteristics of the surface emitting laser and the epitaxial growth methods are discussed, by Shih-Yuan Wang, Kenneth H. Hahn, Michael R.T. Tan, Yu-Min D. Houng, pg 67-71

Generating Short-Wavelength Light Using a Vertical-Cavity Laser Structure. Second-harmonic generation from a GaAs/AlAs vertical cavity fabricated on a (311)B GaAs substrate has been demonstrated. The experimental results and a theoretical analysis show that a GaAs/AlAs vertical cavity optimized both for efficient confinement of the fundamental power and for quasi-phase-matching can offer efficient second-harmonic generation, by Shigeru Nakagawa, Danny E. Mars, Norihide Yamada, pg 72-75

A New, Flexible Sequencer Architecture for Testing Complex Serial Bit Streams. Based on a generic model of serial communication systems, this architecture dramatically reduces the time needed to program functional and in-circuit tests for devices with serial interfaces. It is implemented in a new Serial Test Card and Serial Test Language for the HP 3070 family of broad test systems, by Christopher B. Cain, James L. Benson, Robert E. McAuliffe, pg 76-90. ATE.

Shortening the Time to Volume Production of High-Performance Standard Cell ASICs. Coding guidelines for behavioral modeling and a process for generating wire load models that satisfy most timing constraints early in the design cycle are some of the techniques used in the design process for standard cell ASICs, by Jay D. McDougal, William E. Young, pg 91-96

A Framework for Insight into the Impact of Interconnect on 0.35-mm VLSI Performance. A design and learning tool called AIM (advanced interconnect modeling) provides VLSI circuit and technology designers with the capability to model, optimize, and scale total delay in the presence of interconnect, by Prasad Raje, pg 97-104

Glossary, pg 97

Synthesis of 100% Delay Fault Testable Combinational Circuits by Cube Partitioning. High-performance systems require rigorous testing for path delay faults. A synthesis algorithm is proposed that produces a 100% path delay fault testable function with a minimal set of test pins, by William K. Lam, pg 105-109

Better Models or Better Algorithms? Techniques to Improve Fault Diagnosis. the simple stuck-at-fault model paired with a complex fault diagnosis algorithm is compared against the bridging fault model paired with a simple fault diagnosis algorithm to determine which approach produces the best fault diagnosis in CMOS VLSI circuits, by Robert C. Aitken, Peter C. Maxwell, pg 110-116

Bridging and Stuck-At Faults, pg 110

Potential Detection, pg 115

Authors February 1995: Douglas [Doug] M. Baney, Wayne V. Sorin, Edgar Leckel, Jurgen Sang, Rolf Muller, Clemens Ruck, Christian Hentschel, Tirumala [Rangu] Ranganath, Michael [Mike] J. Ludowise, William [Bill] H. Perez, Tim L. Bagwell, Brian L. Heffner, Paul R. Hernday, Siegmar Schmidt, Halmo Fischer, David M. Braun, Luis M. Fernandez, Greg D. LeCheminant, Dennis J. Derickson, Patricia [Patti] A. Beck, Julie E. Fouguet, Forrest G. Kellert, Gary R. Trott, Susan R. Sloan, Christopher [Chris] M. Miller, David [Dave] J. McQuate, Frank A. Maier, Harald Seeger, Peter R. Robrish, Christopher [Chris] J. Madden, Rory L. Van Tuyl, William [Rick] R. Trutna, Jr., Michael R. T. Tan, Kenneth H. Hahn, Yu-Min D. Houng, Shih-Yuan [S. Y.] Wang, Shigeru Nakagawa, Danny [Dan] E. Mars, Norihide Yamada, Robert [Bob] E. McAuliffe, James L. Benson, Christopher [Chris] B. Cain, Jay D. McDougal, William E. Young, Prasad Raje, William K. Lam, Robert C. Aiken, Peter C. Maxwell, pg 117-123

April 1995 v.46 n.2

Cover: An artistic rendition of the interconnection between the three main VLSI chips that make up the hardware architecture for the HP 9000 Model 712 workstation. The die photos are for the PA 7100LC processor, the graphics chip and the LASI chip.

A Low-Cost, High-Performance PA-RISC Workstation with Built-In Graphics, Multimedia, and Networking Capabilities. Designing as a set the three VLSI components that provide the core functions of CPU, I/0, and graphics for the HP 9000 Model 712 workstation balanced performance and cost and simplified the interfaces between components, allowing designers to create a system with high performance at a low cost, by Roger A. Pearson, pg 6-11

The PA 7100LC Microprocessor: A Case Study of IC Design Decisions in a Competitive Environment. Engineering design decisions made during the early stages of a product’s development have a critical impact on the product’s cost, time to market, reliability, performance and success, by David W. Quint, William L. Walker, Patrick Knebel, Mick Bass, pg 12-22

Design Methodologies for the PA 7100LC Microprocessor. Product features provided in the PA 7100LC are strongly connected to the methodologies developed to synthesize, place and route, simulate, verify and test the processor chip, by Mick Bass, D. Douglas Josephson, Duncan Weir, Terry W. Blanchard, Daniel L. Halperin, pg 23-35

An I/O System on a Chip. The heart of the I/O subsystem for the HP 9000 Model 712 workstation is a custom VLSI chip that is optimized to minimize the manufacturing cost of the system while maintaining functional compatibility and comparable performance with existing members of the Series 700 family, by Brian K. Arnold, Joseph F. Orth, Curtis R. McAllister, Anthony L. Riccio, Frank J. Lettang, Thomas V. Spencer, pg 36-42

An Integrated Graphics Accelerator for a Low-Cost Multimedia Workstation. Designing with a system focus and extracting as much performance and functionality as possible from available technology results in a highly integrated graphics chip that consumes very little board area and power and is 50% faster and five times less expensive than its predecessor, by Paul Martin, pg 43-50. HP 9000 Model 712.

HP Color Recovery Technology. HP Color Recovery is a technique that brings true color capability to interactive, entry-level graphics devices having only eight color planes, by Anthony C. Barkans, pg 51-59

True Color, pg 52

Real-Time Software MPEG Video Decoder on Multimedia-Enhanced PA 7100LC Processors. With a combination of software and hardware optimizations, including the availability of PA-RISC multimedia instructions, a software video player running on a low-end workstation is able to play MPEG compressed video at 30 frames/s, by John P. Beck, Joel Lamb, Ruby B. Lee, Kenneth E. Severson, pg 60-68

Overview of the Implementation of the PA 71000LC Multimedia Enhancements, pg 66-67

HP TeleShare: Integrating Telephone Capabilities on a Computer Workstation. Using off-the-shelf parts and a special interface ASIC, an I/0 card was developed that provides voice, fax, and data transfer via a telephone line for the HP 9000 Model 712 workstation, by S. Paul Tucker, pg 69-74

Call Progress, DTMF Tones, and Tone Detection, pg 73

Product Design of the Model 712 Workstation and External Peripherals. A product design without fasteners and the use of environmentally friendly materials and low-cost parts with integrated functions provides excellent manufacturability, customer ease of use, and product stewardship, by Arlen L. Roesner, pg 75-78

Development of a Low-Cost, High-Performance, Multiuser Business Server System. Using leveraged technology, an aggressive system team, and clearly emphasized priorities, several versions of low-end multiuser systems were developed in record time while dramatically improving the product’s availability to customers, by Karen L. Murillo, Dennis A. Bowers, Gerard M. Enkerlin, pg 79-84. HP 9000 Series 800 Model Ex5, HP 3000 Series 9×8.

HP Distributed Smalltalk: A Tool for Developing Distributed Applications. An easy-to-use object-oriented development environment is provided that facilitates the rapid development and deployment of multiuser, enterprise-wide distributed applications, by Eileen Keremitsis, Ian J. Fuller, pg 85-92

A Software Solution Broker for Technical Consultants. A distributed client-server system gives HP’s worldwide technical consultants easy access to the latest HP and non-HP software products and tools for customer demonstrations and prototyping, by Manny Yousefi, Wulf Rehder, Adel Ghoneimy, pg 93-101

HP Software Solution Broker Accessible Products, pg 98

Bugs in Black and White: Imaging IC Logic Levels with Voltage Contrast. Voltage contrast imaging allows visual tracking of logical level problems to their source on operating integrated circuits, using a scanning electron microscope. This paper presents an overview of voltage contrast and the methods developed to image the failure of dynamic circuits in the floating-point coprocessor of the HP PA 7100LC processor chip, by Jack D. Benzel, pg 102-106

Component and System Level Design-for-Testability Features Implemented in a Family of Workstation Products. Faced with testing over twenty new ASIC components going into four different workstations and multiuser computer models, designers formed a team that developed a common system-level design-for-testability (DFT) architecture so that subsystem parts could be shared without affecting the manufacturing test flow, by Michael Ricchetti, Bulent I. Dervisoglu, pg 107-113

Authors April 1995: Roger A. Pearson, Mick Bass, Patrick Knebel, David W. Quint, William [Will] L. Walker, Terry W. Blanchard, D. Douglas [Doug] Josephson, Duncan Weir, Daniel [Dan] L. Halperin, Thomas [Tom] V. Spencer, Frank J. Lettang, Curtis R. McAlister, Anthony L. Riccio, Joseph [Joe] F. Orth, Brian K. Arnold, Paul Martin, Anthony [Tony] C. Barkans, Ruby B. Lee, John P. Beck, Joel Lamb, Kenneth [Ken] E. Severson, S. Paul Tucker, Arlen L. Roesner, Dennis A. Bowers, Gerard M. Enkerlin, Karen L. Murillo, Eileen Keremitsis, Ian J. Fuller, Manny Yousefi, Adel Ghoneimy, Wulf Rehder, Jack D. Benzel, Bulent I. Dervisoglu, Michael [Mike] Ricchetti, pg 114-118

June 1995 v.46 n.3

Cover: Heating a fused silica capillary in preparation for blowing a bubble in the capillary to improve detection sensitivity in capillary electrophoresis.

Capillary Electrophoresis: A Product of Technological Fusion. An introduction to capillary electrophoresis (CE), its different forms, and its applications, and the history of CE research at HP, leading to the new HP CE instrument described in this issue, by Robert R. Holloway, pg 6-9

A New High-Performance Capillary Electrophoresis Instrument. This instrument automates the CE separation process with high reproducibility of analytical results such as peak areas and migration times. A diode array detector with an optimized optical path including a new extended lightpath capillary provides spectral information with high detection sensitivity. The liquid handling and sample injection systems are designed for flexibility and usability, by Fred Strohmeiery, pg 10-19. G1600A.

Capillary Electrophoresis Applications, by Martin L. Verhoef, pg 12-13

HP CE Technology Transfer, by Alfred Maute, pg 16

Industrial Design of the HP CE Instrument, by Raoul Dinter, pg 18-19

A High-Sensitivity Diode Array Detector for On-Column Detection in Capillary Electrophoresis. The small peak volumes in CE demand special optical design to maximize sensitivity. High light throughput, good stray light suppression, and precise alignment are necessary. The diode array detector design focused on good matching of the illumination system and the spectrometer, precise alignment of the capillary and optical elements, and mechanical and thermal stability, by Patrick Kaltenbach, pg 20-24. HP CE.

Capillary Handling in the HP Capillary Electrophoresis Instrument. Capillaries are encased in cassettes for easy replacement and connections are made automatically when a cassette is installed. Air cooling of the capillary eliminates leak problems and lower costs. Vials containing samples and electrolyte are automatically lifted from a tray to either end of the capillary, by Hans-Peter Zimmermann, pg 25-31. HP CE.

Rapid Prototyping for the HP CE Project, by Martin Bauerle, pg 28-29

Sample Injection in HP CE. For flushing or conditioning the capillary or injecting a sample, air pressures or different values and durations are applied. The injection system provides precise closed-loop control of the integral of the air pressure over time for either direction of fluid flow. The replenishment system automates the exchange of used electrolytes for fresh ones, using a special double-needle design, by Werner Schneider, pg 32-35

HP CE Separation Control Electronics and Firmware. The HP CE instrument consists of a PC and a base unit consisting of detection and separation subunits. Methods are developed on the PC and downloaded to the base unit for independent execution. The control electronics and firmware of the separation subunit takes care of tray and vial movement, capillary voltage, current and power control, capillary temperature control, diagnostics, and related data capture, by Franz Bertsch, Klaus Witt, Fritz Bek, pg 36-43

A User Interface for Capillary Electrophoresis. The graphical user interface of the HP CE instrument is designed to be easily understood by users familiar with other separation methods but new to CE. It provides for method programming and simulation and for visualization of the status of the instrument and the running analysis, by Klaus Witt, Alwin Ritzmann, pg 44-49. ChemStation.

Development of a Common ChemStation Architecture, by Herbert Wiederoder, pg 46

Reproducibility Testing of the HP CE Instrument. The final chemical test developed for the HP CE instrument implicitly checks various instrument functions by determining the reproducibility of migration time and peak area measurements for well-defined chemical samples. The injection type was selected by testing four different types in a series of reproducibility tests. The final test can be used in production, at a customer site, or for teaching CE classes, by Ulrike Jegle, pg 50-56

The Impact of Column Technology on Protein Analysis by Capillary Electrophoresis: Surface Coatings and Analytical Approaches for Assessment. To avoid unwanted interactions between proteins being analyzed and the surface of the fused silica CE capillary, the surface must be deactivated. Four approaches to surface deactivation for protein analysis are presented. A method for determining the extent of protein absorption is discussed, by Monika Dittmann, Sally A. Swedberg, pg 57-61

A New High-Sensitivity Capillary Electrophoresis Detector Cell and Advanced Manufacturing Paradigm. By circumventing laminar flow while expanding the cross section of the analyte, this detector cell greatly increases both the sensitivity and the linearity of capillary electrophoresis. Manufacturing is made feasible by an advanced computer-controlled miniature lathe using machine vision, by Richard P. Tella, Gary B. Gordon, Henrique A. S. Martins, pg 62-70

HP Disk Array: Mass Storage Fault Tolerance for PC Servers. In the process of offering a new technology to the marketplace the expertise of the user is often not considered. The HP Disk Array offers RAID technology with special installation and configuration features tailored for ease of use, by Tom A. Skeie, Michael R. Rusnack, pg 71-81

An Overview of Raid Technology, pg 74

COBOL SoftBench: An Open Integrated CASE Environment. With the aid of a mouse and a menu-driven interface, COBOL programmers new to the UNIX operating system can improve their productivity with a tightly integrated toolset that includes an editor, compiler, debugger, profiler, and other software development tools, by Cheryl Carmichael, pg 82-87

Development and Use of Electronic Schematic Capture in the Specification and Simulation of a Structured-Custom ASIC. ASIC designers must sometimes provide the ASIC vendor with documentation describing the data path of the chip and its relationship to the control portion. This paper describes a method and attendant tools that facilitate the employment of commonly available electronic schematic capture software to ensure that the documentation given to the ASIC vendor always matches the Verilog HDL descriptions used by the ASIC designers for simulation, by David A. Burgoon, pg 88-91

Design and Development of a 120-MHz Bus Interface Block Using Standard Cells and Automatic Place and Route Tools. The RW_IO block runs at 120 MHz and interfaces the master memory controller chip’s 60-MHz core with the 120-MHz processor bus drivers. A design approach using standard cells, automatic place and route tools, and a powerful database management and build tool was used to construct the RW_IO block. This approach was chosen over a full custom or data-path solution because of its reduced risk and the flexibility of the design tools, by Robert E. Ryan, pg 92-95

Authors June 1995: Robert [Bob] R. Holloway, Fred Strohmeier, Patrick Kaltenbach, Hans-Peter Zimmermann, Werner Schneider, Fritz Bek, Franz Bertsch, Klaus Witt, Alwin Ritzmann, Ulrike Jegle, Sally A. Swedberg, Monika Dittmann, Gary B. Gordon, Richard [Rich] P. Tella, Henrique A. S. Martins, Tom A. Skeie, Michael R. Rusnack, Cheryl Carmichael, David [Dave] A. Burgoon, Robert [Bob] E. Ryan, pg 96-98

August 1995 v.46 n.4

Cover: Time-critical applications are represented as brightly colored data packets as opposed to the blue normal-priority data

Introduction to 100VG-AnyLAN and the IEEE 802.12 Local Area Network Standard. 100VG-AnyLAN provides a 100-Mbit/s data rate with guaranteed bandwidth and maximum access delay for time-critical applications such as multimedia, using existing building wiring. It uses demand priority protocol. Developed by Hewlett-Packard and now supported by over 30 companies ranging from integrated circuit vendors to systems suppliers, demand priority is well on its way to becoming the IEEE 802.12 standard, by Alan R. Albrecht, Patricia A. Thaler, pg 6-12. AdvanceStack.

Cable Types, pg 7

Other Network Technologies, pg 10

Demand Priority Protocol. In multiple-hub networks, demand priority ensures fairness of access for all nodes and guarantees access time for multimedia applications, by Alan R. Albrecht, Michael P. Spratt, Patricia A. Thaler, Gregory C. A. Watson, pg 13-17. IEEE 802.12, 100VG-AnyLAN.

Network Protocol Layers, pg 15

Physical Signaling in 100VG-AnyLAN. A physical layer has been developed for demand priority local area networks that accommodates different cable types by means of different physical medium dependent (PMD) sublayers. The major goal was to provide 100-Mbit/s transmission on existing cables, including Category 3, 4 and 5 UTP, STP, and multimode optical fiber, by Alistair N. Coles, David G. Cunningham, Steven G. Methley, Daniel J. Dove, Joseph A. Curcio, Jr., pg 18-26

Cross Talk in Unshielded Twisted-Pair Cables, pg 19-20

Multilevel Signaling, pg 21

Cross Talk Analysis, pg 22

Optical-Fiber Links for 100VG-AnyLAN, by Del Hanson, pg 26

Coding in 100VG-AnyLAN. A 5B/6B coding scheme in which five data bits are encoded into six-bit codewords is used in conjunction with offsetting the data on different channels by three bits in quartet signaling. It provides the level of error detection necessary, produces a signal balanced within narrow limits, and restricts strings of consecutive Os or 1s to a maximum length of 6. It is also efficient, by Jonathan Jedwab, Simon E.C. Crouch, pg 27-32

IEEE 802.3 and 802.5 Frame Formats, pg 30

Polynomial Arithmetic and Cyclic Redundancy Checks, pg 31

Multimedia Applications and 100VG-AnyLAN. Networks must guarantee bandwidth for multimedia traffic and must control end-to-end delay and delay jitter (fluctuation in the arrival time of packets). The new campus network, 100VG-AnyLAN, can meet these requirements in many circumstances through the basic operation of the protocol. More flexibility can be obtained through the use of bandwidth allocators and the target transmission time protocol. Until either the Broadband Integrated Services Digital Network (B-ISDN) or reliable Internet protocols become available, the use of dial-up remote bridges with existing WANs can accommodate multimedia traffic in the near term, by Michael P. Spratt, John R. Grinham, pg 33-38

Remote Bridge Example, pg 35

Higher-Level Protocols, pg 36

Related Projects, pg 38

100VG-AnyLAN 15-Port Hub Design. Much of the intelligence and uniqueness of a 100VG-AnyLAN network is concentrated in the hub. Special repeater, transceiver, and end node chips implement the functionality of the HP J2410A AdvanceStack 100VG Hub 15, by Lisa S. Brown, pg 39-42

Invalid Packet Marker, pg 41

HP AccuPage 2.0: A Toolkit for High-Quality Document Scanning. Working with commercially available OCR programs, the image processing transforms used in HP AccuPage 2.0 improve the accuracy of converting scanned images from a variety of documents to editable text and pictures at the same time, by Steven G. Henry, Steven L. Webb, George Prokop, Kevin S. Burke, pg 43-50. Scanners, Optical Character Recognition.

Glossary, pg 45

An 11.8-in Flat Panel Display Monitor. The HP S1010A flat panel display is designed to be a plug-compatible replacement for CRTs used with HP workstations. This compatibility is provided by an interface board that uses the same analog signals that drive the CRTs to create digital signals to drive a high-resolution, high-performance LCD color display, by Tom J. Searby, Bradly J. Foster, Steven J. Kommrusch, David J. Hodge, pg 51-60

Liquid Crystal Display Technology, pg 53

Product Design of the HP S1010A Flat Panel Display, pg 57-58

A Note About VRAMs, pg 59

Applying an Improved Economic Model to Software Buy-versus-Build Decisions. The decision to buy or build software is a business decision that should be made using a sound economic model. A comprehensive economic model has been developed and applied to actual and estimated data to compare the costs of using a third-party software package to the costs of internal development, by Wesley H. Higaki, pg 61-65

Benchmark Standards for ASIC Technology Evaluation. Two benchmark circuits are used for objectively evaluating ASIC supplier performance claims. The method applies first-order equations relating capacitive discharge currents and transistor saturation current to arrive at a technology constant. The method has been used to survey 14 ASIC suppliers with over 76 different technologies. Results are shown for 48 CMOS technologies, by Aloke S. Bhandia, Henry H. W. Lie, Antonio A. Martinez, pg 66-70

Authors August 1995: Alan R. Albrecht, Patricia [Pat] A. Thaler, Michael P. Spratt, Gregory [Greg] C. A. Watson, Alistair N. Coles, David G. Cunningham, Joseph [Joe] A. Curcio, Jr., Daniel [Dan] J. Dove, Steven G. Methley, Simon E. C. Crouch, Jonathan Jedwab, John R. Grinham, Lisa S. Brown, Steve Webb, Steven [Steve] G. Henry, Kevin S. Burke, George Prokop, David [Dave] J. Hodge, Bradly [Brad] J. Foster, Steven [Steve] J. Kommrusch, Tom J. Searby, Wesley [Wes] H. Higaki, Antonio A. Martinez, Aloke S. Bhandia, Henry H. W. Lie, pg 71-74

October 1995 v.46 n.5

Cover: A solid model created and displayed using the HP Precision Engineering SolidDesigner 3D solid modeling system

HP PE/SolidDesigner: Dynamic Modeling for Three-Dimensional Computer-Aided Design. In most solid modeling CAD systems, knowledge of the history of the design is necessary to avoid unanticipated side-effects when making changes. With dynamic modeling, local geometry and topology changes can be made independently of the model creation at any time, using both direct and dimension-driven methods. The core components enabling dynamic modifications are the tool body and the relation solver, by Klaus-Peter Fahlbusch, Thomas D. Roser, pg 6-13. Precision Engineering Systems, 3D.

User Interaction in HP PE/SolidDesigner. The HP PE/SolidDesigner user interface is modeled after the successful, easy-to-use, easy-to-learn interface of earlier HP CAD products. All commands are coded as Common Lisp action routines. A user interface builder helps command programmers by hiding details of the X Window System and the OSF/Motifä graphical user interface. Prototyping was done using a specially developed Lisp-based interface to OSF/Motif called HLCX, by Markus Kuhl, Berthold Hug, Gerhard J.Walz, pg 14-23

Enhancements in Blending Algorithms. This article describes a rounding operation for a 3D CAD boundary representation (B-Rep) solid model. Complex combinations of convex and concave edges are handled predictably and reliably. At vertices the surfaces are smoothly connected by one or more surface patches. An algorithm for the creation of blending surfaces and their integration into the model is outlined. The sequence of topological modifications applied to the solid model is illustrated by examples including some special case handling, by Stefan Freitag, Karsten Opitz, pg 24-34

Open Data Exchange with HP PE/SolidDesigner. Surface and solid data can be imported from HP PE/ME30 and exchanged with systems supporting the IGES, STEP, and ACIS formats. Imported data coexists with and can be manipulated like native data, by Wolfgang Klemm, Gerhard J. Walz, Peter J. Schild, Hermann J. Ruess, pg 35-50

Providing CAD Object Management Services through a Base Class Library. HP PE/SolidDesigner’s data structure manager makes it possible to save a complex 3D solid model and load it from file systems and databases. Using the concepts of transactions and bulletin boards, it keeps track of changes to a model, implements an undo operation, and notifies external applications of changes, by Claus Brod, Max R. Kublin, pg 51-60

Exception Handling and Development Support, pg 55

Freeform Surface Modeling. There are two methods for creating freeform surfaces in HP PE/SolidDesigner: blending and lofting. This article describes the basics of lofting. The geometry engine, which implements the lofting functionality, uses a single-data-type implementation for its geometric interface, but takes a multiple-data-type, hybrid approach internally, by Michael Metzger, Sabine Eismann, pg 61-68

Common Lisp as an Embedded Extension Language. A large part of HP PE/SolidDesigner’s user interface is written in Common Lisp. Common Lisp is also used as a user-accessible extension language, by Jens Kilian, Heinz-Peter Arndt, pg 69-73. PE/ME10, PE/ME30, CAD.

Boolean Set Operations with Solid Models. The Boolean engine of HP PE/SolidDesigner applies standard and nonstandard Boolean set operations to solid models to perform an impressive variety of machining operations. Parallel calculation boosts performance, especially with multiprocessor hardware, by Peter H. Ernst, pg 74-79

Fighting Inaccuracies: Using Perturbation to Make Boolean Operations Robust, pg 78-79

A Microwave Receiver for Wide-Bandwidth Signals. The HP 71910A wide-bandwidth receiver extends modular spectrum analyzer operation for more effective measurements on modern communications and radar signals, by Robert J. Armantrout, pg 80-88

Firmware Design for Wide-Bandwidth IF Support and Improved Measurement Speed, by Thomas A. Rice, pg 84-85

The HP 89400 Series Vector Signal Analyzers, by Robert T. Cutler, pg 87

An IF Module for Wide-Bandwidth Signals. The HP 70911A IF module provides the HP 71910A receiver with wideband demodulation and variable bandwidths up to 100 MHz, while maintaining the gain accuracy of a spectrum analyzer, by Leonard M. Weber, Terrence R. Noe, Christopher E. Stewart, and Robert J. Armantrout, pg 89-103

The Log Weighted Average for Measuring Printer Throughput. The log weighted average balances the different time scales of various plots in a test suite. It prevents an overemphasis on plots that take a long time to print and allows adjustments according to the expected user profile weighting. It is based on percentage changes rather than absolute plot times, by John J. Cassidy, Jr., pg 104-106. DeskJet 1600C.

Authors October 1995: Klaus-Peter Fahlbusch, Thomas D. Roser, Berthold Hug, Gerhard J. Walz, Markus Kuhl, Stefan Freitag, Karsten Opitz, Peter J. Schild, Wolfgang Klemm, Hermann J. Ruess, Claus Brod, Max R. Kublin, Michael Metzger, Sabine Eismann, Jens Kilian, Heinz-Peter Arndt, Peter H. Ernst, Robert [Bob] J. Armantrout, Terrence [Terry] R. Noe, Christopher [Chris] E. Stewart, Leonard M. Weber, John [Jack] J. Cassidy, Jr., pg 107-110

December 1995 v.46 n.6

Cover: A highly internetworked distributed computing environment made up of clients and servers is shown in the background. In the foreground is the software architecture for one pair of client and server systems.

DCE: An Environment for Secure Client/Server Computing. The Open Software Foundation’s Distributed Computing Environment provides an infrastructure for developing and executing secure client/server applications that are portable and interoperable over a wide range of computers and networks, by Michael M. Kong, pg 6-15

Adopting DCE Technology for Developing Client/Server Applications. HP’s information technology community has adopted DCE as the infrastructure for developing client/server information technology applications. The team developing the DCE service has discovered that putting an infrastructure like DCE in place in a legacy environment is more than just technology and architecture, by Samuel D. Horowitz, Paul Lloyd, pg 16-22

DCE Directory Services. The DCE directory services provide access for applications and users to a federation of naming systems at the global, enterprise and application levels, by David Truong, Michael M. Kong, pg 23-27

X/Open Federated Naming. The X/Open Federated Naming (XFN) specification defines uniform naming interfaces for accessing a variety of naming systems. XFN specifies a syntax for composite names, which are names that span multiple naming systems, and provides operations to join existing naming systems together into a relatively seamless naming federation, by Elizabeth A. Martin, pg 28-33

HP Integrated Login. HP Integrated Login coordinates the use of security systems and improves the usability of computer systems running the HP-UX operating system, by Navaneet Kumar, Lawrence J. Rose, Jane B. Marcus, pg 34-40

The DCE Security Service. A security protocol consisting of encryption keys, authentication credentials, tickets, and user passwords is used to provide secure transmission of information between two transacting parties in a DCE client/server enterprise, by Frederic Gittler, Anne C. Hopkins, pg 41-48

Glossary, pg 42

An Evolution of DCE Authorization Services. One of the strengths of the Open Software Foundation’s Distributed Computing Environment is that it allows developers to consider authentication, authorization, privacy, and integrity early in the design of a client/server application. The HP implementation evolves what DCE offers to make it easier for server developers to use, by Deborah L. Caswell, pg 49-54

An Object-Oriented Application Framework for DCE-Based Systems. Using the Interface Definition Language compiler and the C++ class library, the HP OODCE product provides objects and abstractions that support the DCE model and facilitate the development of object-oriented distributed applications, by Luis M. Maldonado, Mihaela C. Gittler, Michael Z. Luo, pg 55-60

Glossary, pg 60

HP Encina/9000: Middleware for Constructing Transaction Processing Applications. A transaction processing monitor for distributed transaction processing applications maintains the ACID (Atomicity, consistency, isolation and durability) properties of the transactions and provides recovery facilities for aborting transactions and recovering from system or network failures, by Pankaj Gupta, pg 61-74

Glossary, pg 65

Object-Oriented Perspective on Software System Testing in a Distributed Environment. A flexible object-oriented test system was developed to deal with the testing challenges imposed by software systems that run in distributed client/server environments, by Stephen J. McFarland, David S. Levin, Mark C. Campbell, J. Scott Southworth, Ana V. Kapetanakis, David J. Miller, David K. Hinds, pg 75-81

The Object Management Group’s Distributed Object Model, pg 76

Object-Oriented Programming, pg 79

A New, Lightweight Fetal Telemetry System. The HP Series 50 T fetal telemetry system combines both external and internal monitoring of the fetus in a small, lightweight transmitter that is easy and comfortable for the patient to carry. It is useful for monitoring in labor, monitoring of high-risk patients, monitoring in transit, antepartum nonstress testing, and monitoring in the bath, by Jurgen W. Hausmann, Michelle Houghton Jagger, Andreas Boos, Gunter W. Paret, pg 82-93

Zero Bias Detector Diodes for the RF/ID Market. Hewlett Packard’s newest silicon detector diodes were developed to meet the requirements for receiver service in radio frequency identification tags. These requirements include portability, small size, long life, and low cost, by Rolando R. Buted, pg 94-98

Backscatter RF/ID Systems, pg 95

Authors December 1995: Michael [Mike] J. Kong, Paul Lloyd, Samuel [Sam] D. Horowitz, David T. Truong, Elizabeth [Liza] A. Martin, Jane B. Marcus, Navaneet Kumar, Lawrence [Larry] J. Rose, Frederic Gittler, Anne C. Hopkins, Deborah [Debbie] L. Caswell, Mihaela [Mickey] C. Gittler, Michael Zhijing Luo, Luis M. Maldonado III, Pankaj Gupta, Mark [Marcus] C. Campbell, David K. Hinds, Ana V. Kapetanakis, Stephen [Steve] J. McFarland, David S. Levin, David [Dave] J. Miller, J. Scott Southworth, Andreas Boos, Michelle Houghton Jagger, Gunter W. Paret, Jurgen W. Hausmann, Rolando R. Buted, pg 99-102

Index: Volume 46 January 1995 through December 1995. PART 1: Chronological Index, pg 103-104. PART 2: Subject Index, pg 105-110. PART 3: Product Index, pg 111. PART 4: Author Index, pg 111-112