February 1992 v.43 n.1
Cover: An artist’s rendition of an analog oscilloscope display and an HP 54600A oscilloscope display of the output of a circuit designed to synchronize an asynchronous event such as a keypress to a microprocessor clock.
Low-Cost, 100-MHz Digitizing Oscilloscopes. The HP 54600 Series oscilloscopes combine the convenience, familiarity, and display responsiveness of analog oscilloscopes with the features, accuracy, and measurement power of a digital architecture, by Robert A. Witte, pg 6-11
A High Throughput Acquisition Architecture for a 100-MHz Digitizing Oscilloscope. Two custom integrated circuits offload functions from the system microprocessor to increase waveform throughput and give the HP 54600 digitizing oscilloscopes the “look and feel” of an analog oscilloscope, by Daniel P. Timm, Matthew S. Holcomb, pg 11-20
Sample Rate and Display Rate in Digitizing Oscilloscopes, by Robert A. Witte, pg 18-19
A Fast, Built-In Test System for Oscilloscope Manufacturing. Following a verification strategy instead of a screening or characterization strategy, a special module was designed to replace the computer input/output option module of the HP 54600 Series oscilloscopes. The resulting test system has reduced both equipment costs and test times to one tenth those of previous test systems, by Stuart O. Hall, Jay A. Alexander, pg 21-28
Verification Strategy, pg 22
Stimulus/Response Defect Diagnosis in Production, by Chris J. Magnuson, pg 27
Measuring Frequency Response and Effective Bits Using Digital Signal Processing Techniques. Frequency response and effective bits are informative measurements of digital oscilloscope performance, and can be calculated by efficient algorithms using the fast Fourier transform, by Martin B. Grove, pg 29-35. 54600A, 54601A.
Calculating Effective Bits from Signal-to-Noise Ratio, pg 34
Mechanical Design of the HP 54600 Series Oscilloscopes. Simplicity of manufacture and a minimum of parts were the approaches taken to achieve high quality and reliability. Robotic assembly wasn’t a consideration, so rotating motions were often chosen to mate components in final assembly, by Robin P. Yergenson, Timothy A. Figge, pg 36-40
EMC Design of the HP 54600 Series Oscilloscopes. By a combination of electronic circuit design and mechanical shielding techniques, the design meets German FTZ standards and, with optional shielding, most U.S. military standards for electromagnetic compatibility, by Kenneth D. Wyatt, pg 41-45
Digital Oscilloscope Persistence. Autostore, a storage technique for monochrome digital storage oscilloscopes, displays historical traces at half intensity and the most recent, or live, trace at full intensity. The technique allows new ways of viewing signals, by James A. Kahkoska, pg 45-47
A High-Resolution, Multichannel Digital-to-Analog Converter for Digital Oscilloscopes. This 16-bit, 16 channel DAC is used for microprocessor adjustment of fourteen dc signals that control the analog section of the main oscilloscope board in the HP 54601A digitizing oscilloscope. It also provides a high-accuracy dc reference for calibrating the vertical gain, by Grosvenor H. Garnett, pg 48-56
Using the High Resolution, Multichannel DAC in the HP 54601A Oscilloscope, by Mark P. Schnaible, pg 54-55
Comparing Analog and Digital Oscilloscopes for Troubleshooting. The analog oscilloscope has remained the troubleshooter’s instrument of choice even though the digital oscilloscope has replaced it for laboratory analysis. However, the analog oscilloscope has limitations, especially in digital troubleshooting, by Jerald B. Murphy, pg 57-59. 54600.
Authors February 1992: Robert [Bob] A. White, Mathew [Matt] S. Holcomb, Daniel [Dan] P. Timm, Stuart O. Hall, Jay A. Alexander, Martin [Marty] B. Grove, Robin [Rob] P. Vergenson, Timothy [Tim] A. Figge, Kenneth [Ken] D. Wyatt, James A. Kahkoska, Grosvenor [Grove] H. Garnett, Jerald [Jerry] B. Murphy, John McShane, William [Bill] W. Crandall, pg 60-61
An Introduction to Neural Nets. Unlike conventional algorithms, neural net algorithms can learn the mapping between input and output. Neural nets represent information in a distributed, rather than local, way, and can have different topologies depending on the application. This paper explains these features, lists major application areas, and briefly discusses hardware and software for development, by John McShane, pg 62-65
Design Challenges for Distributed LAN Analysis. The design of a distributed local area network management system is primarily a problem of data reduction, data transmission, and data presentation. HP ProbeView software and LanProbe monitors continuously monitor the health of an Ethernet or IEEE 802.3 network to allow the diagnosis of complicated problems without dispatched equipment, by William W. Crandall, pg 66-76
Poor Network Partitioning, pg 76
April 1992 v.43 n.2
Cover: A view of a VXIbus module and the backplane of a VXIbus mainframe
VXIbus: A Standard for Test and Measurement System Architecture. The VXIbus standard defines an open architecture that allows instrumentation and processors from various manufacturers to operate together within a single chassis or mainframe, by Lawrence A. DesJardin, pg 6-14. VMEbus.
The HP VXIbus Mainframes, pg 9-10
VXIbus Terminology, pg 13
The VXIbus From an Instrument Designer’s Perspective. HP has defined a set of internal standards to compensate for some missing aspects of the VXIbus standard that are critical to instrument design, by Gregory A. Hill, Steven J. Narciso, pg 15-23. IEEE 488.2.
Examples of Message-Based VXIbus Instruments, by Don Smith, Harald Mattes, Helmut Sennewald, Tony Lymer, pg 20-21
Small, Low Cost Mainframe with a Register-Based Interface, by Von Campbell, pg 22
Design of Mainframe Firmware in an Open Architecture Environment. Compatibility, portability, expandability, usability, scalability, and compliance with SCPI are some of the attributes designed into HP’s VXIbus mainframe firmware, by Paul B. Worrell, pg 24-28
Real Time Multitasking of Instruments in the VXIbus Command Modules. The operating system in HP’s command modules uses two reentrant processes to handle communication between the user and instruments on the VXIbus, by Christopher P. Kelly, pg 29-34
VXI Programming in C. A library of C functions provides functionality that makes it easier for test program developers to create applications that communicate with HP-IB and VXIbus instruments, by Lee Atchison, pg 35-40
Achieving High Throughput with Register-Based Dense Matrix Relay Modules. With an onboard FIFO buffer and register-based programming, HP’s VXIbus dense matrix relay modules provide high throughput and a downsized, low-cost solution to matrix switching, by James B. Durr, Sam S. Tsai, pg 41-51. E1465A, E1466A, E1467A.
Mass Interconnect for VXIbus Systems. The HP 75000 family of VXIbus products includes a set of interconnect hardware that enables automatic test system developers to mount DUTs easily to HP’s VXIbus mainframe, by Calvin L. Erickson, pg 52-58
A Manufacturing-Oriented Digital Stimulus/Response Test Instrument. This digital functional tester consists of pattern I/0, timing, and command modules configured in a VXIbus mainframe. The maximum pattern rate is 20 MHz and pin-to-pin skew is less than 6 ns, by David P. Kjosness, pg 59-68. 75000 Model D20.
Digital Test Development Software for a VXIbus Tester. This software provides ease of use and direct control for the complex hardware of the HP 75000 Model D20 tester. It uses a spreadsheet paradigm and separates the programming of pattern data from that of timing, by Kenneth A. Ward, pg 69-74. E1496A.
The VXIbus in a Manufacturing Test Environment. Engineers at HP’s Loveland Instrument Division have found that using the VXIbus and the SCPI programming language provides benefits such as reduced test development time and system support costs, by Larry L. Carlson, Wayne H. Willis, pg 75-77. SCPI, Standard Commands for Programmable Instruments.
Authors April 1992: Lawrence [Larry] A. DesJardin, Gregory [Greg] A. Hill, Steven [Steve] J. Narciso, Paul B. Worrell, Christopher [Chris] P. Kelly, Lee Atchison, James [Jim] B. Durr, Sam S. Tsai, Calvin L. Erickson, David [Dave] P. Kjosness, Kenneth [Ken] A. Ward, Wayne H. Willis, Larry L. Carlson, Bieter Scherer, William [Bill] E. Strasser, James [Jim] D. McVey, Wayne M. Kelly, Michael [Mike] C. Fischer, Michael [Mike] J. Schoessow, Peter Tong, David [Dave] L. Barnard, James [Jim] A. Thalmann, Henry Black, Koichi Yanagawa, Michael [Mike] P. Moore, Eric N. Gullerud, pg 77-80
The Peak Power Analyzer, a New Microwave Tool. Gallium arsenide sensor design, a new calibration approach, switched amplification and processing of the envelope signals, leveraged digital oscilloscope technology, and microprocessor control provide calibration-free, accurate pulsed microwave power measurements, by Wayne M. Kelly, William E. Strasser, James D. McVey, Dieter Scherer, pg 81-89
Multilayer Shielding Protects Microvolt Signals in High-Interference Environment, by James L. Bertsch, Charles W. Cook, pg 84
GaAs Technology in Sensor and Baseband Design. In the HP 8990A peak power analyzer design, the detector diodes for the sensors are GaAs planar doped barrier diodes, and the switches in the switchable-gain baseband amplifier use GaAs FETs, by Michael J. Schoessow, Michael C. Fischer, Peter Tong, pg 90-94
Harmonic Errors and Average versus Peak Detection, by Michael C. Fischer, pg 94
Automatic Calibration for Easy and Accurate Power Measurements. Changes in input power, carrier frequency, and sensor temperature are automatically compensated for. The user is not required to disconnect the sensor from the device under test and connect it to a calibration source, by James A. Thalmann, David L. Barnard, Henry Black, pg 95-100. 8990A.
Testing the Peak Power Analyzer Firmware, by Jayesh K. Shah, pg 99
An Advanced 5-Hz-to-500-MHz Network Analyzer with High Speed, Accuracy, and Dynamic Range. A three-processor design provides a measurement speed of 400 microseconds per point, fast enough to keep up with manual adjustments. Maximum frequency resolution is 0.001 Hz. Dynamic accuracy is ±0.05 dB in amplitude and ±0.3 degree in phase. Sensitivity of the three receiver channels is -130 dBm, and dynamic range is 110 dB or 130 dB, depending on the sweep mode, by Koichi Yanagawa, pg 101-109. 8751A.
A High-Performance Measurement Coprocessor for Personal Computers. This plug-in card brings test and measurement coprocessing power to ISA (Industry Standard Architecture) personal computers with greater calculation speed and better HP-IB performance than its predecessor. It also has DMA capability, by Mike Moore, Eric N. Gullerud, pg 110-116. 82324A.
Measurement Coprocessor ASIC, pg 112-113
Measurement Coprocessor History, pg 114
June 1992 v.43 n.3
Cover: An artist rendition of the transformation that take place when source code through register reassociation and software pipelining compiler optimizations
HP-UX Operating System Kernel Support for the HP 9000 Series 700 Workstations. Because much of the Series 700 hardware design was influenced by the system’s software architecture, engineers working on the kernel code were able to make changes to the kernel that significantly improved overall system performance, by Jeffrey R. Glasson, Karen Kerschen, pg 6-10
An Example of the FTEST Instruction, pg 10
Providing HP-UX Kernel Functionality on a New PA-RISC Architecture. To ensure customer satisfaction and produce a high-performance, high-quality workstation on a very aggressive schedule, a special management structure, a minimum product feature set, and a modified development process were established, by Dawn L. Yamine, Donald E. Bollinger, Frank P. Lemmon, pg 11-14. 9000 Series 700.
New Optimizations for PA-RISC Compilers. Extensions to the PA-RISC architecture exposed opportunities for code optimizations that enable compilers to produce code that significantly boosts the performance of applications running on PA-RISC machines, by Robert C. Hansen, pg 15-23
Link Time Optimizations, by Carl Burch, pg 22
HP 9000 Series 700 FORTRAN Optimizing Preprocessor. By combining HP design engineering and quality assurance capabilities with a well-established third party product, the performance of Series 700 FORTRAN programs, as measured by key workstation benchmarks, was improved by more than 30%, by Daniel J. Magenheimer, Alan C. Meyer, Sue A. Meloy, Robert A. Gottlieb, pg 24-32
Vector Library, pg 29-30
Register Reassociation in PA-RISC Compilers. Optimization techniques added to PA-RISC compilers result in the use of fewer machine instructions to handle program loops, by Vatsa Santhanam, pg 33-38
Software Pipelining in the PA-RISC Compilers. The performance of programs with loops can be improved by having the compiler generate code that overlaps instructions from multiple iterations to exploit the available instruction-level parallelism, by Sridhar Ramakrishnan, pg 39-45
Shared Libraries for HP-UX. Transparency is the main contribution of the PA-RISC shared library implementation. Most users can begin using shared libraries without making any significant changes to their existing applications, by Michelle A. Ruscetta, Cary A. Coutant, pg 46-53
Deferred Binding, Relocation, and Initialization of Shared Library Data, by Marc Sabatella, pg 52
Integrating an Electronic Dictionary into a Natural Language Processing System. This paper discusses the types of electronic dictionaries available and the trends in electronic dictionary technology, and provides detailed discussion of particular dictionaries. It describes the incorporation of one of the electronic dictionaries into Hewlett-Packard’s natural language understanding system and discusses various computer applications that could use the technology now available, by Diana C. Roberts, pg 54-65
Authors June 1992: Karen Kerschen, Jeffrey R. Glasson, Frank P. Lemmon, Donald [Don] E. Bollinger, Dawn L. Yamine, Robert [Bob] C. Hansen, Daniel [Dan] J. Magenheimer, Robert [Bob] A. Gottlieb, Alan C. Meyer, Sue A. Meloy, Vatsa Santhanam, Sridhar Ramakrishnan, Cary A. Coutant, Michelle A. Ruscetta, Diana C. Roberts, Dale D. Russell, Susan S. Spach, Ronald [Ron] W. Pulleyblank, pg 65-67
Application of Spatial Frequency Methods to Evaluation of Printed Images. Contrast transfer function methods, applied in pairwise comparisons, differentiated between print algorithms, dot sizes, stroke widths, resolutions (dpi), smoothing algorithms, and toners. Machine judgments based on these methods agreed with the print quality judgment of a panel of trained human observers, by Dale D. Russell, pg 68-75
Parallel Raytraced Image Generation. Simulations of an experimental parallel processor architecture have demonstrated that four processors can provide a threefold improvement in raytraced image rendering speed compared to sequential rendering, by Ronald W. Pulleyblank, Susan S. Spach, pg 76-83
August 1992 v.43 n.4
Cover: The PCX-S chipset for the Apollo 9000 Series 700 workstations includes a CPU, a floating-point-co-processor, and a memory and system bus controller
Midrange PA-RISC Workstations with Price/Performance Leadership. The HP 9000 Models 720, 730 and 750 workstations achieve exceptional performance ratings on industry-standard benchmarks through a combination of a high CPU clock rate (up to 66 MHz) and tuning of the subsystem, compiler, and operating system designs. This article presents an overview of the hardware design, by Andrew J. DeBaets, Kathleen M. Wheeler, pg 6-11
HP 9000 Series 700 Workstation Firmware, by Deborah A. Savage, pg 9
VLSI Circuits for Low-End and Midrange PA-RISC Computers. The major VLSI chips for the HP 9000 Series 700 workstations include a central processing unit with 577,000 transistors, a floating-point coprocessor with 640,000 transistors, and a memory and input/output controller with 185,000 transistors, by Thomas O. Meyer, Craig A. Gleason, Mark A. Forsyth, Leith Johnson, Steven T. Mangelsdorf, pg 12-22
PA-RISC Performance Modeling and Simulation, by Richard G. Fowles, pg 21
ECL Clocks for High-Performance RISC Workstations. In the HP 9000 Series 700 workstations, clock signals are distributed using differential ECL circuits, and the VLSI chips have CMOS inputs operating at ECL levels. Critical clock delay signals are routed on 50-ohm striplines on printed circuits board inner layers, by Frank J. Lettang, pg 23-25
HP 9000 Series 700 Input/Output Subsystem. Integrated on a single 8.5-by-11 inch I/0 board is hardware support for the SCSI, the Centronics parallel printer interface, two RS-232 ports, the IEEE 802.3 LAN, the HP-HIL, four audio tone generators, and a real-time clock. An application-specific IC serves as I/0 subsystem controller, by Daniel Li, Audrey B. Gore, pg 26-33
Design Verification of the HP 9000 Series 700 PA-RISC Workstations. First a high-level system model was stimulated and compared with a reference machine running both HP standard and pseudorandom test programs. Then the same tests were run on hardware prototypes. All chips were able to boot the operating system on first silicon, by Steve W. LaMar, Gregory D. Burroughs, Ali M. Ahi, Chi-Yen R. Lin, Audrey B. Gore, Alan L. Wiemann, pg 34-42
HP Standard PA-RISC Test Programs, pg 35
Simulation Toolset, pg 36
Debugging Tools, pg 39
Metrics, pg 41
Mechanical Design of the HP 9000 Models 720 and 730 Workstations. The CPU board, I/0 board, graphics board, power supply, mass storage tray, and EISA board assembly are designed as easily accessible modules to support the design goals of low cost, accessibility, serviceability, and manufacturability. The appearance is new, attractive, and compatible with existing HP computer products, by John P. Hoppal, Arlen L. Roesner, pg 43-48
Meeting Manufacturing Challenges for PA-RISC Workstations. To meet the time-to-market goals for the HP 9000 Series 700 workstations, major contributions were made in design for manufacturability and in expediting standard processes. One manufacturing operation installed a new surface mount production facility and developed a new printed circuit production process simultaneously, by Kevin W. Allen, Paul Roeber, Samuel K. Hammel, Spencer M. Ure, Anna M. Hargis, pg 49-54
High-Performance Designs for the Low-Cost PA-RISC Desktop. This paper presents the processor, memory, graphics, multimedia, and built-in core I/0 design of the new HP 9000 Models 705 and 710 entry-level, scalable PA-RISC workstations. The use of a buffered CPU/memory interconnect is important for scaling the high-frequency, high-performance processor design to the entry-level desktop, by John A. Dykstal, Don C. Soltis, Jr., Robert J. Hammond, Craig R. Frink, pg 55-63
Low-Cost Plain-Paper Color Inkjet Printing. The HP DeskWriter C and DeskJet 500C are based on advanced thermal inkjet technology in the form of a 300-dpi three-color inkjet print cartridge. The printers and software drivers that use this cartridge were developed on an aggressive one-year schedule, by Daniel A. Kearl, Michael S. Ard, pg 64-68
Thermal Inkjet Review, or How Do Dots Get from the Pen to the Page, by James P. Shields, pg 67
Ink and Print Cartridge Development for the HP DeskJet 500C/DeskWriter C Printer Family. A new trichamber print cartridge allows the low-cost HP DeskJet printer platform to print in color. The ink vehicle, dyes, dye concentrations, and interactions had to be carefully traded off to optimize performance with respect to color bleed, color saturation, composite black production, edge acuity, drying time, and resistance to crusting, by Daniel A. Kearl, Loren E. Johnson, Craig Maze, James P. Shields, pg 69-76
Color Science in Three Color Inkjet Print Cartridge Development, by John M. Skene, pg 71-72
Making HP Print Cartridges Safe for Consumers Around the World, by Michael L. Holcomb, pg 76
Automated Assembly of the HP DeskJet 500C/DeskWriter C Color Print Cartridge. Roughly 60% of the assembly technology had to be developed especially for the color print cartridge. Plastic welding, adhesive dispensing, TAB circuit staking, and ink fill were among the challenges, by Mark C. Huth, Lee S. Mason, pg 77-83
Color Inkjet Print Cartridge Ink Manifold Design, by Gregory W. Blythe, pg 82-83
Adhesive Material and Equipment Selection for the HP DeskJet 500C/DeskWriter C Color Print Cartridge. The adhesive joins the printhead to the cartridge body and maintains color ink separation at the interface. The encapsulant protects the electrical bonds. Special equipment was designed to dispense these materials with high precision in very small volumes, by Terry M. Lambright, Douglas J. Reed, pg 84-86
Machine Vision in Color Print Cartridge Production. In production of the tricolor print cartridges for the HP DeskJet 500C and DeskWriter C printers, machine version is used for filter stake inspection, adhesive and encapsulant dispenser calibration, structural adhesive inspection, and automatic print quality evaluation, by Michael J. Monroe, pg 87-92
HP DeskWriter C Printer Driver Development. Running on the host computer, the driver provides all of the intelligent formatting, rasterizing, color matching, and dithering for this affordable black and color printer, by William J. Allen, Steven O. Miller, Toni D. Courville, pg 93-102
An Interactive User Interface for Material Requirements Planning. For planners and buyers in the manufacturing business environment, HP MRP Action Manager is an online, interactive tool that automates many of the traditional paper-intensive activities of material requirements planning, by Barbara J. Williams, Alvina Y. Nishimoto, William J. Gray, pg 103-110. Action Manager for NewWave.
HP MRP Action Manager Project Management, pg 108
Authors August 1992: Andrew [Andy] J. DeBaets, Kathleen [Kathy] M. Wheeler, Mark A. Forsyth, Craig A. Gleason, Leith Johnson, Steven [Steve] T. Mangelsdorf, Thomas [Tom] O. Meyer, Frank J. Lettang, Daniel Li, Ali M. Ahi, Gregory [Greg] D. Burroughs, Audrey B. Gore, Steve W. LaMar, Chi-Yen [Robert] R. Lin, Alan L. Wiemann, John P. Hoppal, Arlen L. Roesner, Kevin W. Allen, Samuel [Kelley] K. Hammel, Anna Marie Hargis, Paul Roeber, Spencer [Spence] M. Ure, John A. Dykstal, Craig R. Frink, Robert [Bob] J. Hammond, Don C. Soltis, Jr., Daniel [Dan] A. Kearl, Michael [Mike] S. Ard, Craig Maze, Loren E. Johnson, James [Jay] P. Shields, Lee S. Mason, Mark C. Huth, Douglas [Doug] J. Reed, Terry M. Lambright, Michael [Mike] J. Monroe, William [Will] J. Allen, Toni D. Courville, Steven O. Miller, Alvina Y. Nishimoto, William [Bill] J. Gray, Barbara J. Williams, pg 111-115
October 1992 v. 43 n.5
Cover: the HP 4980 Network Advisor can be connected to a network like any other node to monitor the health of the network. This rendition depicts a token ring network with several workstations and the Network Advisor connected to it.
The HP Network Advisor: A Portable Test Tool for Protocol Analysis. This network protocol analysis tool combines expert system technology with a comprehensive set of network statistics and protocol decodes to speed problem resolution for token ring and Ethernet network, by Edmund G. Moore, pg 6-10. 4980.
Network Advisor Product Enhancement Philosophy, pg 9
Embedding Artificial Intelligence in a LAN Test Instrument. The knowledge and processes used by a skilled LAN troubleshooter are built into an interactive expert system application that runs on HP 4980 Series Network Advisor protocol analyzers, by Rod Unverrich, Stephen Witt, Scott Godlew, pg 11-21. 4980.
The User Interface for the HP 4980 Network Advisor Protocol Analyzer. A PC-based, object-oriented software architecture forms the underpinning for the HP 4980 Network Advisor’s user interface, by Thomas A. Doumas, pg 22-28
Object-Oriented Design and Smalltalk, pg 24
The Forth Interpreter, by Robert L. Vixie, pg 24
The Network Advisor Analysis and Real-Time Environment. The user interface and protocol decode applications of the HP 4980 Network Advisor use the services of a software platform that provides real-time protocol analysis and an interface to the network under test, by Sunil Bhat, pg 29-33
Network Advisor Protocol Analysis: Decodes. The decodes feature of the Network Advisor allows users to traverse from a high-level summary of protocol information to a bit-level interpretation of the protocol data, by Rona J. Prufer, pg 34-40. 4980.
Mechanical Design of the HP 4980 Network Advisor. The package design for the Network Advisor was guided by the electrical, mechanical, and ergonomic requirements of a PC-based protocol analyzer, by Kenneth R. Krebs, pg 41-47
The Microwave Transition Analyzer: A New Instrument Architecture for Component and Signal Analysis. The microwave transition analyzer brings time-domain analysis to RF and microwave component engineers. A very wide-bandwidth, dual-channel front end, a precisely uniform sampling interval, and powerful digital signal processing provide unprecedented measurement flexibility, including the ability to measure magnitude and phase transitions as fast as 25 picoseconds, by David J. Ballo, John A. Wendler, pg 48-62
Frequency Translation as Convolution, pg 61
Design Considerations in the Microwave Transition Analyzer. Digital signal processing is used extensively to improve the performance of the microwave sampler, the sample-rate synthesizer and the high-speed analog-to-digital converter, and to extract and display input signal characteristics in both the time domain and the frequency domain, by John A. Wendler, Michael Dethlefsen, pg 63-71. 71500A.
A Visual Engineering Environment for Test Software Development. Software development for computer-automated testing is dramatically eased by HP VEE, which allows a problem to be expressed on the computer using the conceptual model most common to the technical user: the block diagram, by Douglas C. Beethe, William L. Hunt, pg 72-77. VEE.
Object-Oriented Programming in a Large System, by William L. Hunt, pg 76
Developing an Advanced User Interface for HP VEE. Simplicity and flexibility were the primary attributes that guided the user interface development. Test programs generated with HP VEE can have the same advanced user interface as HP VEE itself, by William L. Hunt, pg 78-83. Visual Engineering Environment.
HP VEE: A Dataflow Architecture. HP VEE is an object-oriented implementation. Its architecture strictly separates views from the underlying models. There are two types of models: data models and device models. Special devices allow users to construct composite devices, by Douglas C. Beethe, pg 84-88. Visual Engineering Environment.
A Performance Monitoring System for Digital Telecommunications Networks. This system collects CCITT G.821 performance statistics on CEPT 2, 8, 34, and 140-Mbit/s data streams and alarm data on network elements. A demux capability permits monitoring of tributary streams within a data stream. Data is collected nonintrusively by peripheral units, which are modular VXIbus systems, by Alberto Vallerini, Fernando M. Secco, Giovanni Nieddu, pg 89-99. E3560.
Authors October 1992: Edmund [Ed] G. Moore, Scott Godlew, Rod Unverrich, Stephen [Steve] Witt, Thomas [Tom] A. Doumas, Sunil Bhat, Rona J. Prufer, Kenneth [Ken] R. Krebs, David J. Ballo, John A. Wendler, Michael [Mike] Dethlefsen, Douglas [Doug] C. Beethe, William [Bill] L. Hunt, Giovanni [Gianni] Nieddu, Fernando M. Secco, Alberto Vallerini, Chu-Sun [Chu] Yen, Richard [Rick] C. Walker, Patrick [Pat] T. Petruno, Cheryl Stout, Benny W. H. Lai, William [Bill] J. McFarland, pg 100-102
G-Link: A Chipset for Gigabit-Rate Data Communication. Two easy-to-use IC chips convert parallel data for transmission over high-speed serial links. A special encoding algorithm ensures dc balance in the transmitted data stream. A binary-quantized phase-locked loop is used for clock recovery. An on-chip state machine manages link startup automatically, by Cheryl Stout, William J. McFarland, Richard C. Walker, Benny W. H. Lai, Chu-Sun Yen, Patrick T. Petruno, pg 103-116
Bang-Bang Loop Analysis, by Richard W. Walker, pg 110
December 1992 v.43 n.6
Cover: The pen carriage of the HP DesignJet large-format thermal inkjet drafting plotter is shown with a DesignJet plot.
A Large-Format Thermal Inkjet Drafting Plotter. The HP DesignJet drafting plotter combines the low cost of pen plotters with the speed of electrostatic plotters. Throughput is almost independent of drawing complexity. The plotter uses the same roll and sheet media as pen plotters, and in roll mode, automatically cuts and stack plots for unattended operation, by John F. Meyer, Samuel A. Stodder, Robert A. Boeller, Victor T. Escobedo, pg 6-15
DesignJet Plotter User Interface Design: Learning the Hard Way about Human Interaction, by P. Jeffrey Wield, pg 12
Electronic and Firmware Design of the HP DesignJet Drafting Plotter. High-performance vector-to-raster conversion and print engine control are provided by a RISC processor, two single-chip processors, and three custom integrated circuits. Development of the electronics and firmware made extensive use of emulation and simulation, by Anne P. Kadonaga, James R. Schmedake, Iue-Shuenn Chen, Alfred Holt Mebane IV, pg 16-23
Pen Alignment in a Two-Pen, Large-Format, Inkjet Drafting Plotter. Misalignments are found by using a quad photodiode sensor to measure test patterns printed on the media. Scan-direction errors are corrected by timing adjustments. Media-direction errors are corrected algorithmically and mechanically, by Robert D. Haselby, pg 24-27. DesignJet.
DesignJet Plotter Chassis Design: A Concurrent Engineering Challenge. Instead of the expensive prestraightened slider rods used in previous designs to form the guideway for the pen carriage, the DesignJet chassis uses rods that are straightened during assembly and held in place by a low-cost rigid structure. The chassis components, assembly process, and assembly tooling had to be developed concurrently, by Timothy A. Longust, pg 28-31
DesignJet Plotter End Covers Produced by Coinjection, by Steven R. Card, pg 31
DesignJet Plotter Mechanical Architecture Development Process. By investing several months in designer communication before beginning detailed prototype design, an architecture was developed that was subsequently never changed, allowing the project to reach manufacturing release a month early. Costs for most subsystems were lower than expected, by Chuong Ta, David M. Petersen, pg 32-34
Improved Drawing Reliability for Drafting Plotters. The SurePlot drawing system, a feature of the HP DraftMaster Plus drafting plotter, significantly enhances drawing reliability and unattended plotting ability. The system is based on a noncontact color optical line sensor that verifies the writing of the pens, by Isidre Rosello, Joan Uroz, Josep Giralt Adroher, Robert W. Beauchamp, pg 35-41
Average User Plot, pg 36
Acceptable Quality Level Index, pg 37
An Automatic Media Cutter for a Drafting Plotter. This simple, reliable, low-cost cutter is a classical rotating and linear blade design. It requires no separate drive motors and does not interfere with normal plotting performance. To quantify its performance, cut quality parameters and measurement methods were defined, by David Perez, Josep Abella, Ventura Caamano Agrafojo, pg 42-48. DraftMaster Plus.
Definitions and Measurement Procedures for Cut Quality Parameters, pg 46-47
Reengineering of a User Interface for a Drafting Plotter. An existing user interface has been successfully reengineered and plotter usability enhanced by selecting, combining, and adapting software prototype techniques and standard software development methodologies, by Jordi Gonzalez, Jaume Ayats Ardite, Carles Castellsague Pique, pg 49-55. DraftMaster Plus.
A Multiprocessor HP-UX Operating System for HP 9000 Computers. The system supports up to four processors in the HP 9000 Model 870 computer, significantly increasing online transaction processing (OLTP) performance without degrading uniprocessor performance, by Douglas V. Larson, Kyle A. Polychronis, pg 56-61
Next-Generation Multiprocessor HP-UX, pg 58
Advances in Integrated Circuit Packaging: Demountable TAB. State-of-the-art IC packaging, particularly with RISC architecturess, demands performance at a high lead count. This paper presents some of the fundamental topics in IC packaging, formulates the principal criteria by which single-chip IC packages are judged, and evaluates existing industry-standard packages. A new packaging technology is described that addresses the unsatisfied packaging needs of modern digital systems, by Farid Matta, pg 62-77
The EISA Standard for the HP 9000 Series 700 Workstations. The EISA interface on the HP 9000 Series 700 workstations provides a high-performance, expandable architecture that allows peripherals using different I/0 standards to communicate with the system on the same I/0 bus, by Vicente V. Cavanna, Christopher S. Liu, pg 78-82. Extended Industry Standard Architecture.
EISA Cards for the HP 9000 Series 700 Workstations. The EISA specification’s high-performance, burst-cycle protocol for data transfer is provided on the Series 700 EISA cards through the implementation of DMA and EISA bus master interfaces, by David S. Clark, Andrea C. Lantz, Christopher S. Liu, Thomas E. Parker, Joseph H. Steinmetz, pg 83-96. Extended Industry Standard Architecture.
Board-Level Simulation of the Series 700 EISA Cards, pg 94-95
Software for the HP EISA SCSI Card. Two software architectures, one offline and the other online, are used to provide EISA SCSI support for the HP 9000 Series 700 workstations, by Bill Thomas, Alan C. Berkema, Eric G. Tausheck, Brian D. Mahaffy, pg 97-108. Extended Industry Standard Architecture.
Update on the SCSI Standard, pg 103-104. See Also: Correction: Two missing lines from page 103, on page 19 in the February 1993 issue
Adapting the NCR 53C710 to Minimize Interrupt Impact on Performance, pg 105
An Architecture for Migrating to an Open Systems Solution. A process and a model have been developed that provide an easy growth path to a client/server, open systems architecture for information technology applications, by Michael E. Thompson, Gregson P. Siu, Jonathan van den Berg, pg 109-114. WSS, Worldwide Support Systems.
Authors December 1992: Robert [Bob] A. Boeller, Samuel [Sam] A. Stodder, John F. Meyer, Victor T. Escobedo, Alfred Holt Mebane IV, James [Jim] R. Schmedake, Iue-Shuenn Chen, Anne Park Kadonaga, Robert [Bob] D. Haselby, Timothy [Tim] A. Longust, David [Dave] M. Petersen, Chuong Ta, Robert W. Beauchamp, Joseph Giralt Adroher, Joan Uroz, Isidre Rosello, Ventura Caamano Agrafojo, David Perez, Josep Abella, Jordi Gonzalez, Jaume Ayats Ardite, Carles Castellsague Pique, Kyle A. Polychronis, Douglas [Doug] V. Larson, Farid Matta, Vicente [Vince] V. Cavanna, Christopher [Chris] S. Liu, David S. Clark, Andrea C. Lantz, Thomas [Tom] E. Parker, Joseph [Joe] H. Steinmetz, Bill Thomas, Alan C. Berkema, Eric G. Tausheck, Brian D. Mahaffy, Michael [Mike] E. Thompson, Gregson P. Siu, Jonathan [Jon] van den Berg, pg 115-119
Index: Volume 43 January 1992 through December 1992. PART 1: Chronological Index, pg 120-122. PART 2: Subject Index, pg 122-126. PART 3: Product Index, pg 127. PART 4: Author Index, pg 127-128.
