1996 – HP Journal Index

February 1996 v.47 n.1

In Memoriam: Barney Oliver, pg 3

Cover: The HP 9000 J/K-class servers and workstations and the HP 3000 Series 9x9KS servers

Symmetric Multiprocessing Workstations and Servers System-Designed for High Performance and Low Cost. A new family of workstations and servers provides enhanced system performance in several price classes. The HP 9000 Series 700 J-class workstations provide up to 2-way symmetric multiprocessing, while the HP 9000 Series 800 K-class servers (technical servers, file servers) and HP 3000 Series 9x9KS business-oriented systems provide up to 4-way symmetric multiprocessing, by Brendan A. Voge, Badir M. Mousa, Loren P. Staley, Matt J. Harline, pg 8-17

K-Class Power System, by Gerald J. Nelson, James K. Koch, pg 16-17

A High-Performance, Low-Cost Multiprocessor Bus for Workstations and Midrange Servers. The Runaway bus, a synchronous, 64-bit, split-transaction, time multiplexed address and data bus, is a new processor-memory-I/O interconnect optimized for one-way to four-way symmetric multiprocessing systems. It is capable of sustained memory bandwidths of up to 768 megabytes per second in a four-way system, by Nicholas S. Fiduccia, William R. Bryg, Kenneth K. Chan, pg 18-24. 9000 K-class, J-class.

Runway Bus Electrical Design Considerations, by Nicholas S. Fiduccia, pg 22-23

Design of the HP PA 7200 CPU. The PA 7200 processor chip is specifically designed to give enhanced performance in a four-way multiprocessor system without additional interface circuits. It has a new data cache organization, a prefetching mechanism, and two integer ALUs for general integer superscalar execution, by Francis X. Schumacher, Gordon P. Kurpanek, Kenneth K. Chan, Cyrus C. Hay, Jason Zheng, John R. Keller, pg 25-33

Verification, Characterization, and Debugging of the HP PA 7200 Processor. To guarantee a high-quality product the HP PA 7200 CPU chip was subjected to functional and electrical verification. This article describes the testing methods, the debugging tools and approaches, and the impact of the interactions between the chip design and the IC fabrication process, by David N. Goldberg, James R. McGee, Thomas B. Alexander, Kent A. Dickey, Akshya Prakash, Nazeem Noordeen, Ross V. La Fetra, pg 34-43

A New Memory System Design for Commercial and Technical Computing Products. This new design is targeted for use in a wide range of HP commercial servers and technical workstations. It offers improved customer application performance through improvements in capacity, bandwidth, latency, performance scalability, reliability, and availability. Two keys to the improved performance are system-level parallelism and memory interleaving, by Thomas R. Hotchkiss, Norman D. Marschke, Richard M. McClosky, pg 44-51. HP 9000 J/K-class, Runway Bus.

Hardware Cache Coherent Input/Output. Hardware cache coherent I/O is a new feature of the PA-RISC architecture that involves the I/O hardware in ensuring cache coherence, thereby reducing CPU and memory overhead and increasing performance, by Helen Nusbaum, Michael K. Traynor, Todd J. Kjos, Brendan A. Voge, pg 52-59. HP 9000 J/K-class, HP PA-RISC.

A 1.0625-Gbit/s Fibre Channel Chipset with Laser Driver. This chipset implements the Fibre Channel FC-0 physical layer specification at 1.0625 Gbits/s. The transmitters features 20:1 data multiplexing with a comma character generator and a clock synthesis phase-locked loop, and includes a laser driver and a fault monitor for safety. The receiver provides the functions of clock recovery, 1:20 data demultiplexing, comma character detection, and word alignment, and includes redundant loss-of-signal alarms for eye safety. A single-chip version with both transmitter and receiver integrated is designed for disk drive applications using the Fibre Channel arbitrated loop protocol, by Benny W.H. Lai, Margaret M. Nakamoto, Richard Dugan, Justin S. Chang, pg 60-67. G-Link chipset, HDMP-1512, HDMP-1514.

Applying the Code Inspection Process to Hardware Descriptions. The code inspection process from the software world has been applied to Verilog HDL (hardware description language) code. This paper explains the code inspection process and the roles and responsibilities of the participants. It explores the special challenges of inspecting HDL, the types of findings made, and the lessons learned from using the process for a year, by Joseph J. Gilray, pg 68-72

Overview of Code-Domain Power, Timing, and Phase Measurements. Telecommunications Industry Association standards specify various measurements designed to ensure the compatibility of North American CDMA (code division multiple access) cellular transmitters and receivers. This paper is a tutorial overview of the operation of the measurement algorithms in the HP 83203B CDMA cellular adapter, which is designed to make the base station transmitter measurements specified in the standards, by Raymond A. Birgenheier, pg 73-93. TIA IS-95/97.

Authors February 1996: Matt J. Harline, Brendan A. Voge, Loren P. Staley, Badir [Bud] M. Mousa, William [Bill] R. Bryg, Kenneth [Ken] K. Chan, Nicholas [Nick] S. Fiduccia, Cyrus [Cy] C. Hay, John R. Keller, Gordon P. Kurpanek, Francis X. Schumacher, Jason Zheng, Thomas [Tom] B. Alexander, Kent A. Dickey, David [Dave] N. Goldberg, Ross V. La Fetra, James [Jim] R. McGee, Nazeem Noordeen, Akshya Prakash, Thomas [Tom] R. Hotchkiss, Norman [Norm] D. Marschke, Richard [Rich] M. McClosky, Todd J. Kjos, Helen Nusbaum, Michael [Mike] K. Traynor, Justin S. Chang, Richard Dugan, Benny W. H. Lai, Margaret M. Nakamoto, Joseph [Joe] J. Gilray, Raymond [Ray] A. Birgenheier,  pg 94-97

April 1996 v.47 n.2

Cover: A screen showing a typical collection of icons, panels, windows, and dialog boxes that make up the graphical user interface of the Common Desktop Environment

A Common Desktop Environment for Platforms Based on the UNIXÒ Operating System. User interface technologies from four companies have been combined to create a single UNIX desktop standard that provides a common look and feel for end users and a common set of tools for system administrators and application developers, by Dana E. Laursen, Jon A. Brewster, Brian E. Cripe, pg 6-11. CDE.

Appendix A: CDE Application Programming Interfaces, pg 11-14

Accessing and Administering Applications in CDE. Setting up transparent access to applications and resources in a highly networked environment is made simpler by facilities that enable system administrators to integrate applications into the CDE desktop, by Anna Ellendman, William R. Yoder, pg 15-23. Common Desktop Environment.

Application Servers and Clients in CDE, pg 22

The CDE Action and Data Typing Services. Several different types of databases and their associated APIs are involved in determining the look and behavior of icons presented in the Common Desktop Environment, by Arthur F. Barstow, pg 24-28

Migrating HP VUE Desktop Customizations to CDE. With CDE becoming the UNIXÒ desktop standard, it is important to allow HP VUE users to preserve their customizations when moving over to the CDE desktop. A set of tools has been developed to make this transactions as complete and effortless as possible, by Molly Joy, pg 29-37. Visual User Environment, Common Desktop Environment.

A Media-Rich Online Help System. Based on an existing fast and easy-to-use online help system, the CDE help system extends this baseline to provide features that will work across all UNIXÒ platforms, by Lori A. Cook, Steven P. Hiebert, Michael R. Wilson, pg 38-49. Common Desktop Environment.

Managing a Multicompany Software Development Project. The development of the Common Desktop Environment version 1.0 involved a joint engineering project between four companies that normally compete in the marketplace, by Robert M. Miller, pg 50-53. CDE, IBM, Sun Microsystems, USL, UNIX.

Design and Development of the CDE 1.0 Test Suite. Testing a product whose parts are being developed in four different environments that have different test tools and test procedures requires setting some rigorous test goals and objectives at the beginning of the project, by Paul R. Ritter, Kristann L. Orton, pg 54-61. CDE, Common Desktop Environment.

Synlib: The Core of CDE Tests. Synlib is an application program interface for creating tests for graphical user interface applications. A collection of Synlib programs, each designed to verify a specific property of the target software, forms a test suite for the application. Synlib tests can be completely platform independent – an advantage for testing the Common Desktop Environment (CDE), which runs on the platforms of the four participating companies, by Sankar L. Chakrabarti, pg 62-65

A Hybrid Power Module for a Mobile Communications Telephone. This article describes a 3.5-watt power module designed for a GSM (Global System for Mobile Communications) handheld telephone. The design features proprietary silicon power bipolar devices, lumped elements for input, interstage, and output matching, thick-film alumina ceramic technology, and laser trimmed bias resistors. High-volume manufacturing was a design requirement, by Melanie M. Daniels, pg 66-72

Automated C-Terminal Protein Sequence Analysis Using the HP G1009A C-Terminal Protein Sequencing System. The HP G1009A is an automated system for the carboxy-terminal amino acid sequence analysis of protein samples. It detects and sequences through any of the twenty common amino acids. This paper describes a number of applications that demonstrates its capabilities, by Jerome M. Bailey, Chad G. Miller, pg 73-82

Abbreviations for the Common Amino Acids, pg 74

Measuring Parasitic Capacitance and Inductance Using TDR. Time-domain reflectometry (TDR) is commonly used as a convenient method of determining the characteristics impedance of a transmission line or quantifying reflections caused by discontinuities along or at the termination of a transmission line. TDR can also be used to measure quantities such as the input capacitance of a voltage probe, the inductance of a jumper wire, the end-to-end capacitance of a resistor, or the effective loading of a PCI card. Element values can be calculated directly from the integral of the reflected or transmitted waveform, by David J. Dascher, pg 83-96

Authors April 1996: Brian E. Cripe, Jon A. Brewster, Dana E. Laursen, Anna Ellendman, William [Bill] R. Yoder, Arthur [Art] F. Barstow, Molly Joy, Lori A. Cook, Stephen [Steve] P. Hiebert, Michael [Mike] R. Wilson, Robert [Bob] M. Miller, Kristann L. Orton, Paul R. Ritter, Sankar L. Chakrabarti, Melanie M. Daniels, Chad G. Miller, Jerome M. Bailey, David [Dave] J. Dascher, pg 97-99

June 1996 v.47 n.3

In Memoriam: David Packard, pg 2

Cover: A rendition of the multiple views of time-correlated data provided by the HP 16505A prototype analyzer

Reducing Time to Insight in Digital System Integration. Digital design teams are facing exponentially growing complexities and need processes and tools that reduce the time needed to gain insight into difficult system integration problems. This article describes modern digital systems in terms of the problems they create in the system integration phase. The debug cycle is described with special emphasis on the “insight loop”, the most time-consuming phase of system integration. A case study from an HP workstation design effort is used to illustrate the principles. A new digital analysis tool, the HP 16505A prototype analyzer, is introduced as a means of solving these vexing problems more quickly by reducing time to insight, by Patrick J. Byrne, pg 6-14

Prototype Analyzer Architecture. The HP 16505A architecture allows multiple concurrent views of acquired logic analysis data. Markers on all views are correlated. The user only needs to place the marker on one view and the markers on the other views automatically relocate. Thus a stack anomaly in one view can be immediately correlated with the software routine causing the violation, by Jeffrey E. Roeca, pg 15-21

Determining a Best-Fit Measurement Server Implementation for Digital Design Team Solutions. Prototype analyzer customers wanted fast throughput, quick answers, a turnkey solution, an affordable base system price, connection to diverse open-systems networks and platforms, and interfaces to a wide variety of tools. An encapsulated measurement server architecture based on a dedicated workstation and a SCSI II interface best fit the requirements, by Gregory J. Peters, pg 22-29. 16505A.

A Normalized Data Library for Prototype Analysis. The goal was that each analysis and display tool to be included in the prototype analyzer should be designed and written only once. Therefore, the data library is designed to normalize the variety of basic logic analyzer data types and the variety of postacquisition data types generated by various analysis tools and to present this data to other analysis and display tools in a standard format, by Mark P. Schnaible, pg 30-37. 16505A.

A Full-Featured PentiumÒ PCI-Based Notebook Computer. The HP OmniBook 5000 computer takes advantage of new technologies such as mobile Pentium, PCI, plug and play, lithium-ion batteries, and hot docking to give users the same capabilities as their desktop computers, by Timothy F. Myers, pg 38-44

Flyback Charger Circuit, pg 42

A Graphing Calculator for Mathematics and Science Classes. The HP 38G calculator allows teachers to direct students and keep them focused while they explore mathematical and scientific concepts. It features aplets, which are small applications that focus on a particular area of the curriculum and can be easily distributed from the teacher’s calculator to the students’, by James A. Donnelly, Feng Yuan, Ted W. Beers, Diana K. Byrne, Robert W. Jones, pg 45-58. HP 38G.

Distributed Software Team, pg 54

Creating HP 38G Aplets. This article explores a simple aplet and shows how to construct an aplet called PolySides, by James A. Donnelly, pg 59-63

HP PalmVue: A New Healthcare Information Product. The HP PalmVue system integrates personal computer, alphanumeric paging, and palmtop computer technology into an effective solution for delivering timely and high-quality patient data to mobile physicians, by Jon D.Waisnor, Allan P. Sherman, Edward H. Schmuhl, pg 64-69. M1490A.

Data Through Paging Technology, pg 68

Constructing An Application Server. In a dynamic networked environment in which there are several hundred workstations and servers there is a constant demand for new versions of software. In this environment software installation procedures must be quick, flexible, and tolerant of change, by Jill E. Swenson, pg 70-75

Interface Translation for Reuse of Assembly-Language Modules in a Two-Language Environment. A mixture of low-level and high-level implementation languages is likely when old modules are reused. In a two-language system, some interfaces must be expressed in both languages. This paper describes the design and implementation of a production-quality software tool that solves this problem for the C programming language, by James R. Buffenbarger, pg 76-81

Authors June 1996: Patrick [Pat] J. Byrne, Jeffrey [Jeff] E. Roeca, Gregory [Greg] J. Peters, Mark P. Schnaible, Timothy [Tim] F. Myers, Ted W. Beers, Diana K. Byrne, James [Jim] A. Donnelly, Robert [Max] W. Jones, Feng Yuan, Edward [Ted] H. Schmuhl, Allan [Al] P. Sherman,  Jon D. Waisnor, Jill E. Swenson, James [Jim] R. Buffenbarger, pg 82-84

August 1996 v.47 n.4

Cover: A computer-colorized and embossed photograph of a cracked 58Bi42Sn solder joint, showing that the brittle fracture of the Bi-rich phase was the cause of the brittle failure of the solder

Implementing the Capability Maturity Model for Software Development. Continuous support for a software development improvement effort requires at least two things: a clearly defined improvement model and success at applying the model in the organization. One HP division was able to apply one such model and achieve measurable success on several product releases, by Douglas E. Lowe, Guy M. Cox, pg 6-14. CMM.

Software Failure Analysis for High-Return Process Improvement Decisions. Software failure analysis and root-cause analysis have become valuable tools in enabling organizations to determine the weaknesses in their development processes and decide what changes they need to make and where, by Robert B. Grady, pg 15-24

HP Press Book Excerpt. Evolutionary Fusion: A Customer-Oriented Incremental Life Cycle for Fusion. Creating and maintaining a consistent set of specifications that result in software solutions that match customer’s needs is always a challenge. A method is described that breaks the software life cycle into smaller chunks so that customer input is allowed throughout the process, by Todd Cotton, pg 25-38

What Is Fusion?, by Derek Coleman, pg 27

Fusion in the Real World, by Ruth Malan, Reed P. Letsinger, pg 37

The Evolutionary Development Model for Software. The traditional waterfall life cycle has been the mainstay for software developers for many years. For software products that do not change very much once they are specified, the waterfall model is still viable. However, for software products that have their feature sets redefined during development because of user feedback and other factors, the traditional waterfall model is no longer appropriate, by Barbara A. Zimmer, Elaine L. May, pg 39-45. EVO, Evolutionary Development.

The Software Initiative Program, pg 42

HP Domain Analysis: Producing Useful Models for Reusable Software. Early software reuse efforts focused on libraries of general-purpose routines or functions. These fine-grained assets did not produce the hoped-for quality and productivity improvements. Recent software reuse efforts have shown that architecture-based, domain-specific reuse can yield greater quality and productivity improvements, by Patricia Collins Cornwell, pg 46-55

Reuse Roles: Producers, Supporters, and Utilizers, pg 50

A Model for Platform Development. For many software and firmware products today, creating the entire architecture and design and all the software modules from the ground up is no longer feasible, especially from the point of view of product quality, ease of implementation and short product development schedules. Therefore, the trend is to create new product versions by intentionally reusing the architecture, design, and code from an established software platform, by Emil Jandourek, pg 56-71

A Decision Support System for Integrated Circuit Package Selection. The package provides signal and power distribution, heat dissipation, and environmental protection for an integrated circuit (IC). The process of selecting a package is complicated by the large number of packaging alternatives with overlapping capabilities. To handle these difficulties, a decision support system was developed. The Package Selection Systems (PASS) combines expert system tools and multiple-attribute decision making techniques. The expert system provides a list of technically feasible alternatives. The multiple-attribute decision making modules are used to rank the alternatives based on nontechnical criteria, by Craig J. Tanner, pg 72-79. MLM, Manufacturingless Manufacturers, MADM.

Cycle Time Improvement for Fuji IP2 Pick-and-Place Machines. Some of the major enhancements are eliminating head contention, reducing or eliminating nozzle changes, supporting user-defined nozzles, supporting large nozzles for holders 2 and 3, and being able to define multiple part data for a given part number. The cycle time improvement exceeds the original goal of 5%, and the result at one surface mount center was more than 16% over hand-created and optimized recipes. The solution helps both the high-volume and the high-mix centers, by Fereydoon Safai, pg 80-83

Reducing Setup Time for Printed Circuit Assembly. In 1994, HP’s Man-Link recipe generation system was enhanced to reduce the time required for setting up pick-and-place machines. This was done by ordering the products to exploit the commonality of parts among them and by creating sequences of setups that differ as little as possible from one another. This paper documents the issues and trade-offs and discusses the potential benefits, by Richard C. Palm, Jr., pg 84-90

Low-Temperature Solders. The application of low-temperature solders in surface mount assembly processes for products that do not experience harsh temperature environments is technically feasible. One single alloy may not be appropriate as a universal solutions, by Hubert A. Vander Plas, Zequn Mei, Helen A. Holder, pg 91-98. EADC, Electronic Assembly Development Center.

Assessment of Low-Temperature Fluxes. The subject of this paper is the evaluation of the wetting balance as a technique for studying the flux activity of newly developed low-temperature solder paste fluxes. The most effective configuration of the wetting balance was the standard configuration with only one change: the PbSn eutectic solder was replaced with a eutectic solder alloy with a melting point of 58°C. Since 58°C is significantly less than the proposed activation temperatures of the solder fluxes, wetting curves as a function of temperature could be studied for each of the fluxes. The resulting data was used to rank the fluxes in terms of the activation requirement, by Helen Holder, Zequn Mei, Russell B. Cinque, Hubert A. Vander Plas, pg 99-103

October 1996 v.47 n.5

Cover: An artistic rendition of telecommunications, showing a satellite antenna in the background and an HP OEMF network map and alarm viewer for a mobile network in the foreground

A Platform for Building Integrated Telecommunication Network Management Applications. Telecommunications companies today are faced with rapid technological change, large heterogeneous environments, and a greater need to provide customers with products that ensure reliable, cost-effective network service. This means that these companies need a platform that has a visionary strategy that enables them to develop standards-compliant network management solutions for a continually changing environment, by Prabha G. Chadayammuri, pg 6-16

Distributed Processing Environment: A Platform for Distributed Telecommunications Applications. Vendors developing applications for a heterogeneous, distributed environment need to be able to build towards a platform that integrates all the management and control functions of distributed computing into a unified software architecture that allows their applications to be available from any point in the network regardless of the system or geographic location, by Trong Nguyen, Frank Quemada, Frank Leong, Satya P. Mylavarabhata, pg 17-21. DPE.

HP OEMF: Alarm Management in Telecommunications Networks. This article explains the HP OpenView Element Management Framework concept, which is based on the HP OpenView Fault Management Platform (FMP) and complements the functionality of the FMP to provide an integrated network management solution. This article also explains the FMP, which facilitates efficient management of alarms in a telecommunications network, and the open APIs provided in the FMP, which allow seamless integration with other applications, by Sujai Hajela, pg 22-30

HP OpenView Event Correlation Services. When a fault occurs in a telecommunications system, it can cause an event storm of several hundred events per second for tens of seconds. HP OpenView Event Correlation Services (ECS) helps operators interpret such storms. It consists of an ECS Designer for the interactive development of correlation rules and an ECS engine for executive of these rules, by Kenneth R. Sheers, pg 31-42

Correlation Node Types, pg 34

Count Node, pg 36

Unless Node, pg 37

Table Node, pg 38

Fact Store and Data Store, pg 39

Annotation, pg 40

A Modeling Toolset for the Analysis and Design of OSI Network Management Objects. To deal with the complexity of network management standards and the increasing demand to deploy network management applications quickly, analysts and designers need a set of tools to help them quickly and easily model, define, and develop new network management objects, by Jacqueline A. Bray, pg 43-49. GDMO, Guidelines for the Definition of Managed Objects.

Appendix A: A Portion of a GDMO Definition for a UNIX Password File, pg 5-51

A Toolkit for Developing TMN Manager/Agent Applications. Developing manager and agent applications for telecommunications network management that conform to standards can be a time-consuming task because of the number of APIs and data types involved in dealing with network data and protocols. The HP OpenView Managed Object Toolkit aids and accelerates the development of these TMN applications, by Lisa A. Speaker, pg 52-61

A Software Toolkit for Developing Telecommunications Application Components. To be effective, application developers must understand the data available to their applications, the operations required to access the data, and the steps required to turn their understanding into an implementation. A prototype development environment has been built that helps the developer explore and understand the data in the Management Information Base (MIB) and construct and deploy pieces of TMN management applications, by Alasdair D. Cox, pg 62-69

Business Process Flow Management and its Application in the Telecommunications Management Network. HP OpenPM is an open, enterprise-capable, object-oriented business process flow management system that manages business activities supporting complex enterprise processes in a distributed heterogeneous computing environment. It is a middleware service that represents a substantial evolution from traditional workflow technologies, by Qiming Chen, James W. Davis, Weimin Du, Ming-Chien Shan, pg 70-76

HP OpenView Agent Tester Toolkit. In developing HP OpenView agents, a major challenge is to develop and test both the agent and the manager simultaneously. To fill this need, the HP OpenView Agent Tester Toolkit generates tests and allows the developer to execute these tests individually or as a set, by Paul A. Stoecker, pg 77-80

Storage Management Solutions for Distributed Computing Environments. Strategies for dealing with the vast amounts of data generated by today’s information technology environments involve more than just larger and larger disk drives. They include the right combination of different storage devices to deal with offline, nearline, and online data storage and scalable management software, by Kelly A. Emo, Reiner Lomb, Roy M. VanDoorn, pg 81-89

Authors October 1996: Prabha G. Chadayammuri, Frank Leong, Satya P. Mylavarabhatla, Trong Nguyen, Frank Quemada, Sujai Hajela, Kenneth [Ken] R. Sheers, Jacqueline [Jackie] A. Bray, Lisa A. Speaker, Alasdair D. Cox, Ming-Chien Shan, James [Jim] W. Davis, Weimin Du, Qiming Chen, Paul A. Stoecker, Reiner Lomb, Kelly A. Emo, Roy M. Vandoorn, Meryem Primmer, Judith [Judy] A. Smith, pg 90-93

An Introduction to Fibre Channel. Fibre Channel is a flexible, scalable, high-speed data transfer interface that can operate over a variety of both copper wire and optical fiber at data rates up to 250 times faster than existing communication interfaces. Networking and I/O protocols, such as SCSI commands, are mapped to Fibre Channel constructs, encapsulated, and transported within Fibre Channel frames, by Meryem Primmer, pg 94-98

Tachyon: A Gigabit Fibre Channel Protocol Chip. The Tackyon chip implements the FC-1 and FC-2 layers of the five-layer Fibre Channel standard. The chip enables a seamless interface to the physical FC-0 layer and low-cost Fibre Channel attachments for hosts, systems, and peripherals on both industry-standard and proprietary buses through the Tachyon system interface. It allows sustained gigabit data throughput at distance options from ten meters on copper to ten kilometers over single-mode optical fiber, by Meryem Primmer, Judith A. Smith, pg 99-112

December 1996 v.47 n.6

New: 1996 Index is available at URL: http://www.hp.com/hpj/index96.html  [sic; url no longer functions]

Cover: A color-graded eye diagram produced by the HP 83480 digital communications analyzer, superimposed on a display of the frequency response of its optical channel

A New Instrument for Waveform Analysis of Digital Communications Signals. The HP 83480 digital communications analyzer combines an optical reference receiver with an oscilloscope and communications measurement firmware. Its measurements meet the requirements of the SONET and SDH fiber-optic communications standards, by Christopher M. Miller, Michael J. Karin, Stephen W. Hinch, pg 6-12

Eye Diagrams and Sampling Oscilloscopes, pg 8-9

Firmware Measurement Algorithms for the HP 83480 Digital Communications Analyzer. Parametric measurements measure waveform properties such as rise time, fall time, overshoot, period, and amplitude on either a pulse waveform or an eye diagram. Mask measurements compare the shape of the waveform to a predefined mask. Eye parameter measurements measure properties that are unique to eye diagrams, such as eye height, eye width, jitter, crossing height, and extinction ration, by Christopher P. Duff, Stephen W. Hinch, Michael G. Hart, pg 13-21

HP Eyeline Display Mode, p 18-19

Design of Optical Receiver Modules for Digital Communications Analysis. These three bit-rate-specific optical plug-in modules are essential components of the HP 83480A Digital Communications Analyzer. They are for data rates of 155/622 Mbits/s, 2.488 Gbits/s, and 9.953 Gbits/s, by Christopher M. Miller, Randall King, Mark J. Woodward, Tim L. Bagwell, Joseph Straznicky, Naily L. Whang, Donald L. Faller, Jr., pg 22-31

Transimpedance Amplifier O/E Converter Design, pg 29

Differential Time-Domain Reflectometry Module for a Digital Oscilloscope and Communications Analyzer. The HP 54754A differential TDR plug-in conjunction with the HP 54750 digital oscilloscope or the HP 83480 digital communications analyzer significantly improves the speed and ease of making critical measurements in today’s high-speed systems, by Michael M. McTigue, Christopher P. Duff, pg 32-36

Frequency Response Measurement of Digital Communications Analyzer Plug-in Modules. It has been extremely difficult to characterize the SONET/SDH standard receiver with tolerances of ±0.3 dB. This paper describes a method for calibrating photoreceiver frequency response with the low inherent uncertainty of the U.S. National Institute of Standards and Technology Nd:YAG heterodyne system and transferring this calibration to a production test system while maintaining a low uncertainty, by Rin Park, Paul D. Hale, pg 37-40

Radially Staggered Bonding Technology. This new approach to fine-pitch integrated circuit bonding entails a new configuration of bonding pads on the die, dual-loop wire bonding, and a new leadframe design that minimizes wire lengths. The approach bypasses the usual obstacles to fine-pitch bonding that arise with the conventional in-line approach, thus providing appreciable die size and cost reduction with a minimal assembly cost penalty, by Rajendra D. Pendse, Rita N. Horner, Fan Kee Loh, pg 41-50

Implementation of Pad Circuitry for Radially Staggered Bond Pad Arrangements. One approach to pushing the limits of wire bonding pitch in IC packages is to use two rows of radially staggered bond pads. This paper discusses the design of pad circuitry to mesh with the radially staggered bond pad arrangement. A test chip that incorporates suitable test structures was designed, fabricated, packaged and tested to verify the viability of the approach, by Rajendra D. Pendse, Fan Kee Loh, Rita N. Horner, pg 51-54

A Miniature Surface Mount Reflective Optical Shaft Encoder. The HEDR-8000 Series encoders provide two-channel medium-resolution encoding performance in a very small SO-8 plastic package. Their small size, reflective operation, and low cost enable customers to design them into applications that were impossible for earlier encoders, such as feedback sensing for the miniature motors used in copiers, cameras, vending machines, and card readers, by Ram S. Krishnan, Thomas J. Lugaresi, Richard Ruh, pg 55-59

The Global Positioning System and HP SmartClock. The U.S. Department of Defense Global Positioning Systems has inherent problems that limit its use as a source of timing. HP SmartClock is a collection of software algorithms that solve or greatly minimize these problems, by John A. Kusters, pg 60-67. GPS.

See Also: Reader Forum: A letter from Dennis D. McCarthy and John A. Kusters regarding “The Global Positioning System and HP SmartClock”, page 132 in the August 1997 issue

Universal Time Coordinated (UTC), pg 65

The Third-Generation HP ATM Tester. Breaking away from the traditional bounds of transmission and protocol analyzers, the HP E5200A broadband service analyzer redefines the way in which the interactions between protocol layers at multiple points in the network are analyzed and presented, leading to the new concept of service analysis, by Stewart W. Day, Thomas F. Cappellari, Geoffrey H. Nelson, pg 68-73

Glossary, pg 69

Managed Objects for Internal Application Control. Managed objects are fundamental to the software architecture of the HP E5200A broadband service analyzer. Typically used to control remote network elements, managed objects are also used internally by the service analyzer’s application to control application objects, by John P. Nakulski, pg 74-78

Macros, pg 77

Developing a Design for Manufacturability Focus. The HP Australian Telecommunication Operation has rapidly evolved from a custom test instrument developer to an operation that develops and produces products in higher volumes. Significant cultural and technological hurdles have been overcome during the transition to an operation focused on design for manufacturability, by John G. Fuller, pg 79-84. ATO.

HP E5200A Broadband Service Analyzer EMC Design, by Cary J. Wright, pg 80-81

HP E5200A Broadband Service Analyzer Surface Mount Assembly, by Wyatt Luce, pg 83

Production Test Strategy for the HP E5200A Broadband Service Analyzer. Boundary scan and built-in self-test are supplemented by conventional testing techniques. Eight discrete levels of testing were implemented, by Cary J. Wright, pg 85-87

Usable Usability. Usability engineering aims to improve a product’s ease of use by focusing on user needs. “Usable usability” also considers the needs of the product developers, by Peter G. Tighe, pg 88-93

Authors December 1996: Stephen [Steve] W. Hinch, Michael [Mike] J. Karin, Michael [Mike] G. Hart, Christopher [Chris] M. Miller, Randall [Randy] King, Mark [Woody] J. Woodward, Tim L. Bagwell, Donald [Don] L. Faller, Jr., Joseph [Joe] Straznicky, Naily L. Whang, Michael [Mike] M. McTigue, Christopher [Chris] P. Duff, Rin Park, Paul D. Hale, Rajendra [Raj] D. Pendse, Rita N. Horner, Fan [Frankie] Kee Loh, Ram S. Krishnan, Thomas [Tom] J. Lugaresi, Richard Ruh, John [Jack] A. Kusters, Stewart W. Day, Geoffrey [Geoff] H. Nelson, Thomas [Frank] F. Cappellari, John P. Nakulski, John G Fuller, Cary J. Wright, Peter [Pete] G. Tighe, pg 94-98