February 1997 v.48 n.1

Cover: The neonatal version of a family of sensors used for monitoring oxygen saturation levels in a patient’s blood

SoftBench 5.0: The Evolution of an Integrated Software Development Environment. The vision and objectives of the original SoftBench product have enabled it to continue to be a leader in the integrated software development market. For example, since SoftBench 1.0 over 80 third-party software tools have been integrated with SoftBench, by Deborah A. Lienhart, pg 6-11

Applying a Process Improvement Model to SoftBench 5.0, by Deborah A. Lienhart, Scott Jordan, pg 8-9

The C++ SoftBench Class Editor. The C++ SoftBench class editor adds automatic code generation capabilities to the class graph of the SoftBench static analyzer. Novice C++ programmers can concentrate on their software designs and have the computer handle C++’s esoteric syntax. Experienced C++ programmers benefit from smart batch editing functionality and by having the computer quickly generate the program skeleton, by Julie B. Wilson, pg 12-15

The SoftBench Static Analysis Database. The static analysis database supports the SoftBench static analyzer and the C++, C, FORTRAN, Pascal, and Ada programming languages. The underlying data is isolated by a complier interface and a tool interface, by Robert C. Bethke, pg 16-18

CodeAdvisor: Rule-Based C++ Defect Detection Using a Static Database. C++ SoftBench CodeAdvisor is an automated error detection tool for the C++ language. It uses detailed semantic information available in the SoftBench static database to detect high-level problems not typically found by compliers. This paper describes CodeAdvisor and identifies the advantages of static over run-time error checking, by Timothy J. Duesing, John R. Diamant, pg 19-21

Using SoftBench to Integrate Heterogeneous Software Development Environments. Migrating from mainframe-based computing to client/server-based computing can result in a heterogeneous collection of machines that do not interoperate, forcing software developers to deal with unfamiliar system commands and systems that cannot share data. A SoftBench control daemon is described that enables developers to integrate heterogeneous computing systems into efficient, tightly coupled software development environments with consistent, easy-to-use graphical user interfaces across all machines, by Stephen A. Williams, pg 22-27

The Supply Chain Approach to Planning and Procurement Management. The supply chain approach models stochastic events influencing a manufacturing organization’s shipment and inventory performance in the same way that a mechanical engineer models tolerance buildup in a new product design. The objectives are to minimize on-hand inventory and optimize supplier response time, by Gregory A. Kruger, pg 28-34. SRT.

Appendix I: Derivation of the Standard Deviation of Demand Given an R-Week Review Period, pg 34

Appendix II: The Expected Value and Variance of On-Hand Inventory when there Are no Restrictions on Minimum Buy Quantities, pg 34

Appendix III: The Expected Value and Variance of On-Hand Inventory when there Are Restrictions on Minimum Buy Quantities, pg 35

Appendix IV: Incorporating SRT (Supplier Response Time) into the Safety Stock Calculations, pg 36-37

Appendix V: Derating the Service Level to Account for Reduced Periods of Exposure to Stock-outs as a Result of Minimum Buy or Economic Order Quantities, pg 37

Appendix VI: Estimating Weekly Demand Uncertainty from Monthly Data, pg 38

Appendix VII: Adjusting Safety Stock to Account for Yield Loss, pg 38

A New Family of Sensors for Pulse Oximetry. This new family of reusable sensors for noninvasive arterial oxygen saturation measurements is designed to cover all application areas. It consists of four sensors: adult, pediatric, neonatal, and ear clip, by Dietmar Miller, Siegfried Kastle, Friedemann Noller, Siegfried Falk, Anton Bukta, Eberhard Mayer, pg 39-53. M1191A, M1192A, M1193A, M1194A.

Volunteer Study for Sensor Calibration, pg 48-49

Neonatal Sensor Clinical Validation, pg 52

Design of a 600-Pixel-per-Inch, 30-Bit Color Scanner. Simply sampling an image at higher resolution will not give the results a customer expects. Other optical parameters such as image sharpness, signal-to-noise ratio, and dark voltage correction must improve to see the benefits of 600 pixels per inch, by Steven L. Webb, Kevin J. Youngers, Michael J. Steinle, Joe A. Eccher, pg 54-61. ScanJet 3c/4c.

Sing to Me, pg 59

Building Evolvable Systems: The ORBlite Project. One critical requirement that HP has learned over the years from building large systems is the need for the system and its components to be able to evolve over time. A distributed object communication framework is described that supports piecewise evolution of components, interfaces, communication protocols, and APIs and the integration of legacy components, by Keith E. Moore, Evan R. Kirshenbaum, pg 62-72

Developing Fusion Objects for Instruments. The successful application of object-oriented technology to real-world problems in a nontrival task. This is particularly true for developers transitioning from nonobject-oriented methods to object-oriented methods. Key factors that improve the probability of success in applying object-oriented methods are selecting an object-oriented method, developing a process definition and continually improving the process, by Antonio A. Dicolen, Jerry J. Liu, pg 73-85

An Approach to Architecting Enterprise Solutions. A frequently mentioned ailment in healthcare information management is the lack of compatibility among information systems. To address this problem, HP’s Medical Products Group has created a high-level model that defines the major architectural elements required for a complete healthcare enterprise information system, by Robert A. Seliger, pg 86-95. MPG.

Components and Objects, pg 88

The Andover Working Group, pg 89

Multiple Interfaces in COM, pg 91

Object-Oriented Customer Education. As customers require more trusted advice to solve their business problems, the choice of education solutions has become a strategic issue that often precedes and directs the choice of technologies, by Wulf Rehder, pg 96-102

Questions about Using Objects, pg 98

Starting an Object-Oriented Project, by Ramesh Balasubramanian, pg 100

Authors February 1997: Deborah [Debbie] A. Lienhart, Julie B. Wilson, Robert [Bob] C. Bethke, Timothy [Tim] J. Duesing, John R. Diamant, Stephen [Steve] A. Williams, Gregory [Greg] A. Kruger, Siegfried Kastle, Friedemann Noller, Siegfried Falk, Anton [Toni] Bukta, Eberhard Mayer, Dietmar Miller, Steven [Steve] L. Webb, Kevin J. Youngers, Michael [Mike] J. Steinle, Joe A. Eccher, Keith E. Moore, Evan R. Kirshenbaum, Antonio [Tony] A. Dicolen, Jerry J. Liu, Rob Seliger, Wulf Rehder, pg 103-106

April 1997 v.48 n.2

Cover: Successively zoomed views of the analog startup waveform of a circuit, captured by the HP 54645D mixed-signal oscilloscope triggering on digital data

A Family of Instruments for Testing Mixed-Signal Circuits and Systems. This entirely new product category combines elements of oscilloscopes and logic analyzers, but unlike previous combination products, these are “oscilloscope first” and logic analysis is the add-on, by Robert A. Witte, pg 6-9. 54645A, 54645D.

Mixed-Signal Microcontroller, by Weis Reid, pg 8

Testing a Mixed-Signal Design Based on a Single-Chip Microcontroller. The HP 54645D mixed-signal oscilloscope simplifies the testing and debugging of microcontroller-based mixed-signal designs with its integrated analog and digital channels, by Jerald B. Murphy, pg 10-12

Design of a Mixed-Signal Oscilloscope. This combination of a digital oscilloscope and a logic timing analyzer provides powerful cross-domain triggering capabilities for capturing signals in mixed-signal environments. MegaZoom technology, consisting of advanced acquisition techniques and dedicated signal processing, maintains display responsiveness while making optimal use of deep sample memory, by Matthew S. Holcomb, Stuart O. Hall, Warren S. Tustin, Patrick J. Burkart, Steven D. Roach, pg 13-22. 54645A/D.

A Cost-Effective Architecture for a 500-MHz Counter for Glitch Trigger, by Steven D. Roach, pg 22

Sustained Sample Rate in Digital Oscilloscopes. At all but a few of the fastest sweep speeds, the acquisition memory depth and not the maximum sample rate determines the oscilloscope’s actual sample rate. Peak detection capability, when used correctly, can make up for acquisition memory shortfalls, by Steven B. Warntjes, pg 23-25

Acquisition Clock Dithering in a Digital Oscilloscope. When a frequency component of the input signal is greater than half the sample rate, aliening can occur. When the oscilloscope is equivalent time sampling, signals that are subharmonics of the sample clock will be poorly displayed. In the HP 54645A/D oscilloscopes, these effects are greatly reduced by dithering the sample clock during and between acquisitions, by Derek E. Toeppen, pg 26-28

An Oscilloscope-Like Logic Timing Analyzer. Market research indicated that some customers doing embedded development preferred to work with oscilloscopes instead of standard logic analyzers. The HP 54620 logic timing analyzer offers many oscilloscope features, including direct-access controls, a highly interactive display, computed measurements, delayed sweep, simplified triggering, and a trace labelmaker, by Steven B. Warntjes, pg 29-33

Oscilloscope/Logic Timing Analyzer Synergy, pg 31

High-Sample-Rate Multiprocessor-Based Oscilloscopes. The HP 54615B and 54616B oscilloscopes blend proprietary high-speed sampling technology with the power of digital signal processing and a proven user interface to deliver usable advanced characterization capability, by R. Scott Brunton, pg 34-36

A Dielectric Spectrometer for Liquid Using the Electromagnetic Induction Method. Key parameters of colloids are often directly related to or can be derived from permittivity or conductivity. Dielectric dispersion analysis (dielectric spectroscopy) yields insights into colloidal properties. A dielectric meter using a new sensing technique has been developed, by Hideki Wakamatsu, pg 37-44. E5050A.

Emulating ATM Network Impairments in the Laboratory. This article discusses a new product for the HP Broadband Series Test System. The HP E4219 ATM network impairment emulator allows telecommunication network and equipment manufacturers to emulate an Asynchronous Transfer Mode network in the laboratory, by Robert W. Dmitroca, Susan G. Gibson, Trevor R. Hill, Luisa Mola Morales, Chong Tean Ong, pg 45-50

A Message Handling System for B-ISDN User-Network Interface Signaling Test Software. B-ISDN user-network interface signaling has many different protocol variants and each of them has tens of different types of messages. The message handling system provides a powerful tool for the developer to easily support these variants and messages in the HP Broadband Series Test System (BSTS), by Satoshi Naganawa, Richard Z. Zuo, pg 51-58

Object-Oriented Network Management Development. As networks continue to proliferate, the need to develop and deploy network management applications has become a critical issue. Two software development tools are described that allow developers to create powerful network management-side applications quickly without necessarily having to be experts on network protocols, by Peter E. Mellquist, Thomas Murray, pg 59-65. SNMP++, SNMPGen, Simple Network Management Protocol.

SNMP,  pg 60

Design of an Enhanced Vector Network Analyzer. A liquid crystal display (LCD) reduces size and weight and has a larger viewing area. TRL (Thru-Reflect-Line) calibration allows measurement of components that do not have coaxial connectors. New software algorithms achieve faster acquisition and frequency tuning of the synthesized source to give faster updates of the measurement data, by Barry A. Brown, Stanley E. Jaffe, Frank K. David, Frederic W. Woodhull II, Richard R. Barg, Joel P. Dunsmore, Douglas C. Bender, pg 66-77. 8720.

Modeling Source Match Effects for Microwave Power Splitter Design, by Joel P. Dunsmore, pg 72-73

Optimization of Interconnect Geometry for High-Performance Microprocessors. The goals of the work presented in this paper were to estimate quantitatively the impact of interconnect technology parameters on the performance of high-end microprocessors and to use this information to optimize the interconnect geometry within the constraints imposed by the process. The 64-bit PA 8000 microprocessor was used as a test case, by Khalid Rahmat, Soo-Young Oh, pg 78-83

Designing, Simulating, and Testing and Analog Phase-Locked Loop in a Digital Environment. In designing a phase-locked loop for use on several HP ASICs, the digital portion of an existing phase-locked loop was transferred to a behavioral VHDL description and synthesized. A behavioral model was written for the analog section to allow the ASIC designers to run system simulations. A new leakage test was developed that has been very effective in screening out process defects in the filter of the original design, by Thomas J. Thatcher, Michael M. Oshima, Cindy Botelho, pg 84-88

Analog Behavioral Modeling and Mixed-Mode Simulation with SABER and Verilog. A description is given of specific analog behavioral modeling and mixed-mode simulation techniques using SABER and Verilog. Full-channel simulations have been carried out on a class I partial response maximum likelihood (PRML) read/write channel chip. Complex analog circuits such as an adaptive feed-forward equalizer, an automatic gain control block, and a phase-locked loop are modeled in detail with SABER MAST mixed-signal behavioral modeling language. A simulation speedup of two orders of magnitude has been achieved compared to SPICE, by Ben B. Sheng, Hugh S. C. Wallace, James S. Ignowski, pg 89-94

Physical Design of 0.35-mm Gate Arrays for Symmetric Multiprocessing Servers. To meet gate density and system performance requirements for the HP Exemplar S-class and X-class technical servers, a physical design methodology was developed for 1.1-million-raw-basic-cell, 0.35-mm CMOS gate arrays. Commercial and ASIC vendor-supplied tools were augmented with internally developed tools to put together a highly optimized physical chip design process, by Lionel C. Bening, Tony M. Brewer, Harry D. Foster, Jeffrey S. Quigley, Robert A. Sussman, Paul F. Vogel, Aaron W. Wells, pg 95-103

Fast Turnaround of a Structured Custom IC Design Using Advanced Design Tools and Methodology. Through the use of several new tools and methodologies, a small team of engineers was able to design and verify a 1.7-million-FET chip in eight months. The tools and methodologies used included a set of guidelines and timing constraints that were met by the customer, a data path compiler, a highly tuned custom multiplier cell that was used in 87 locations, and an automated top-level power connection scheme, by Rory L. Fisher, Stephen R. Herbener, John R. Morgan, John R. Pessetto, pg 104-107. IMACC.

Authors April 1997: Robert [Bob] A. Witte, Jerald [Jerry] B. Murphy, Matthew [Matt] S. Holcomb, Stuart [Stu] O. Hall, Warren S. Tustin, Patrick J. Burkart, Steven [Steve] D. Roach, Steven [Steve] B. Warntjes, Derek E. Toeppen, R. Scott Brunton, Hideki Wakamatsu, Robert W. Dmitroca, Susan G. Gibson, Trevor R. Hill, Luisa Mola Morales, Chong Tean Ong, Satoshi Naganawa, Richard Z. Zuo, Peter E. Mellquist, Thomas [Tom] Murray, Frank K. David, Frederic [Fred] Woodhull II, Richard [Dick] R. Barg, Joel P. Dunsmore, Douglas [Doug] C. Bender, Barry A. Brown, Stanley [Stan] E. Jaffe, Khalid Rahmat, Soo-Young Oh, Thomas [Tom] J. Thatcher, Michael [Mike] M. Oshima, Cindy Botelho, Hugh S. C. Wallace, James [Jim] S. Ignowski, Lionel C. Bening, Tony M. Brewer, Harry D. Foster, Jeffrey [Jeff] S. Quigley, Robert [Bob] A. Sussman, Paul F. Vogel, Aaron W. Wells, Rory L. Fisher, Stephen [Steve] R. Herbener, John R. Morgan, John R. Pessetto, pg 107-112

June 1997 v.48 n.3

Cover: An artistic rendition of the change in the printing model brought on by the Printing Performance Architecture (PPA) implemented in the HP DeskJet 820C. The top figure depicts printing before the PPA where most of the printing logic resides in the printer. The lower figure depicts printing after the PPA where most of the printing logic resides in the host computer.

A Lower-Cost Inkjet Printer Based on a New Printing Performance Architecture. The HP DeskJet 820C printer is the first HP inkjet printer in an evolutionary product plan that takes advantage of computer and operating systems trends to make inkjet printing affordable for more users. The printer’s integrated software, firmware, and digital electronics architecture uses the computational resources in the PC instead of duplicating these resources in the printer, by David J. Shelley, James T. Majewski, Mark R. Thackray, John L. McWilliams, pg 6-11

PPA Printer Software Driver Design. The software driver for the HP DeskJet 820C printer performs many functions that were formerly performed in the printer, including swath cutting, data formatting, and communications. The driver also includes a PCL emulation module for DOS application support, by David M. Hall, Lee W. Jackson, Katrina Heiles, Karen E. Van der Veer, Thomas J. Halpenny, pg 12-21. Printing Performance Architecture.

PPA Printer Firmware Design. Hewlett-Packard’s new Printing Performance Architecture (PPA) includes a significantly reduced set of printer firmware. “Don’t touch the dots” was the firmware designer’s golden rule. This means that the firmware and processor do only mechanism control, I/O, command parsing, status reporting, user interface, and general housekeeping functions, by Erik Kilk, pg 22-30. DeskJet 820C.

PPA Printer Controller ASIC Development. As the first Printing Performance Architecture printer, the HP DeskJet 820C needed a completely new digital controller ASIC design. The chip’s architecture was optimized for the specific requirements of PPA. Concurrent development of hardware and firmware through the use of hardware emulators and attention to regulatory issues during the design helped the product meet all of its requirements on schedule, by John L. McWilliams, Leann M. MacMillan, Bimal Patak, Harlan A. Talley, pg 31-37

Next Generation Inkjet Printhead Drive Electronics. By integrating the functions of four ICs into one new custom IC and then moving all the electronics related to the pens up to the carriage with the pens, significant savings were realized. A simple, low-contact-count, inexpensive flexible cable is used to connect the carriage to the main printed circuit assembly, by Huston W. Rice, pg 38-42. DeskJet 850C.

The PA 7300LC Microprocessor: A Highly Integrated System on a Chip. A collection of design objectives targeted for low-end systems and the legacy of an earlier microprocessor, which was designed for high-volume cost-sensitive products, guided the development of the PA 7300LC processor, by Terry W. Blanchard, Paul G. Tobin, pg 43-47

Configurability of the PA 7300LC, pg 45

Functional Design of the HP PA 7300LC Processor. Microarchitecture design, with attention to optimizing specific areas of the CPU and memory and I/O subsystems, is key to meeting the cost and performance goals of a processor targeted for midrange and low-end computer systems, by Leith Johnson, Stephen R. Undy, pg 48-60

Timing Flexibility, pg 53

High-Performance Processor Design Guided by System Costs. To minimize time to market and keep costs low, the PA 7300LC design was leveraged from a previous CPU, the chip area was reduced, cache RAM arrays with redundancy were added, and high-speed, high-coverage scan testing was added to reduce manufacturing costs, by David C. Kubicek, Thomas J. Sullivan, Amitabh Mehra, John G. McBride, pg 61-68

Verifying the Correctness of the PA 7300LC Processor. Functional verification was divided into presilicon and postsilicon phases. Software models were used in the presilicon phase, and fabricated chips and real systems were used in the postsilicon phase. In both phases the goals were the same – to find design bugs and ensure that customers get the highest quality part possible, by Paul G. Tobin, Duncan Weir, pg 69-72

Random Code Generation, pg 71

An Entry-Level Server with Multiple Performance Points. To address the very intense, high-volume environment of departmental and branch computing, the system design for the D-class server was made flexible enough to offer many price and performance features at its introduction and still allow new features and upgrades to be added quickly, by Lin A. Nease, Kirk M. Bresniker, Charles J. Zacky, Michael J. Greenside, Alisa Sandoval, pg 73-81. HP 9000 Series 800.

A Low-Cost Workstation with Enhanced Performance and I/O Capabilities. Various entities involved in product development came together at different times to solve a design problem, evaluate costs, and make adjustments to their own projects to accommodate the cost and performance goals of the low-cost HP 9000 B-class workstation, by Scott P. Allan, Bruce P. Bergmann, Ronald P. Dean, Dianne Jiang, Dennis L. Floyd, pg 82-88

Testing Safety-Critical Software. Testing safety-critical software differs from conventional testing in that the test design approach must consider the defined and implied safety of the software at a level as high as the functionality to be tested, and the test software has to be developed and validated using the same quality assurance processes as the software itself, by Evangelos Nikolaropoulos, pg 89-94 OmniCare.

Another Approach to Testing: Inspections, pg 92

A High-Level Programming Language for Testing Complex Safety-Critical Systems. Dealing with an enormous amount of data is characteristic of validating complex and safety-critical software systems. ATP, a high-level programming language, supports the validation process. In a patient monitor test environment it has shown its usefulness and power by enabling a dramatic increase in productivity. Its universal character allows it to migrate validation scenarios to different products based on other architectural paradigms, by Andreas Pirrung, pg 95-102

Structural Testing, Random Testing, and Statistical Structural Testing,  pg 97

An Automated Test Evaluation Tool. The AutoCheck program fully automates the evaluation of test protocol files for medical patient monitors. The AutoCheck output documents that the evaluation has been carried out and presents the results of the evaluation, by Jorg Schwering, pg 103-108. AutoTest.

Effective Testing of Localized Software. Testing localized software is a complex and time-consuming task. With the help of the testing tools developed for HP patient monitors, local language validation for these products is fully automated, by Evangelos Nikolaropoulos, Jorg Schwering, Andreas Pirrung, pg 109-111

Authors June 1997, David [Dave] J. Shelley, James Majewski, Mark R. Thackray, David M. Hall, Lee W. Jackson, Katrina Heiles, Karen E. Van der Veer, Thomas [Tom] J. Halpenny, Erik Kilk, John L. McWilliams, Leann M. MacMillan, Bimal Pathak, Harlan A. Talley, Huston [Hugh] W. Rice, Terry W. Blanchard, Paul G. Tobin, Leith Johnson, Stephen [Steve] R. Undy, David C. Kubicek, Thomas [Tom] J. Sullivan, Amitabh Mehra, John G. McBride, Duncan Weir, Lin A. Nease, Kirk M. Bresniker, Charles J. Zacky, Michael [Mike] J. Greenside, Alisa Sandoval, Scott P. Allan, Bruce P. Bergmann, Ronald [Ron] P. Dean, Dianne Jiang, Dennis L. Floyd, Evangelos Nikolaropoulos, Andreas Pirrung, Jorg Schwering, pg 112-116

August 1997 v.48 n.4

Visit our website at http://www.hp.com/hpj/journal.html [sic; url no longer functions], pg 3

Cover: The four-way superscalar HP PA 8000 microprocessor

Four-Way Superscaler PA-RISC Processors. The HP PA 8000 and PA 8200 PA-RISC CPUs feature an aggressive four-way superscalar implementation, speculative executive, and on-the-fly instruction reordering, by Anne P. Scott, Kevin P. Burkhart, Ashok Kumar, Richard M. Blumberg, Gregory L. Ranson, pg 8-15

Design Methodologies and Circuit Design Trade-Offs for the HP PA 8000 Processor. This paper discusses the various design methods used in the PA 8000, specific design techniques for the new packaging technology, the clock distribution scheme, cross-chip signal integrity issues, and some of the new tools and techniques, by Paul J. Dorweiler, Floyd E. Moore, D. Douglas Josephson, Glenn T. Colon-Bonet, pg 16-21

Functional Verification of the HP PA 8000 Processor. The advanced microarchitecture of the HP PA 8000 CPU has many features that presented significant new verification challenges. These include out-of-order instruction execution, register renaming, speculative execution, four-way superscalar operation, decoupled instruction fetch, concurrent system bus interface, and PA-RISC 2.0 architecture enhancements. Enhanced functional verification tools and processes were required to address this microarchitectural complexity, by Steven T. Mangelsdorf, Raymond P. Gratias, Richard M. Blumberg, Rohit Bhatia, pg 22-31

Electrical Verification of the HP PA 8000 Processor. Electrical verification applies techniques from both functional verification and reliability and environmental testing to improve the quality of the CPU. Electrical verification checks that the CPU functions correctly under stressful environmental conditions, well outside the normal operating environment, by John W. Bockhaus, Rohit Bhatia, C. Michael Ramsey, Joseph R. Butler, David J. Ljung, pg 32-39

Shmoo Plot Shapes,  pg 35

Solving IC Interconnect Routing for an Advanced PA-RISC Processor. This paper discusses some important new block routing technologies that were required for the HP PA 8000 processor chip. These technologies are implemented in a new block routing system called PA_Route, by James C. Fong, Hoi-Kuen Chan, Martin D. Kruckenberg, pg 40-45

Global Routing – A Block-Level Problem,  pg 42

Detailed Routing Methods, pg 43

Intelligent Networks and the HP OpenCall Technology. The HP OpenCall product family is a portfolio of computer-based telecommunications platforms designed to offer a foundation for advanced network services based on intelligent network concepts. This article concentrates on the HP OpenCall service executive platform, service management platform, and service creation environment, by Tarek Dehni, John O’Connell, Nicolas Raguideau, pg 46-57

Standardization – A Phased Approach, pg 49

HP OpenCall SS7 Platform. The HP OpenCall SS7 platform allows users to build computer-based signaling applications connected to the SS7 signaling network, by Denis Pierrot, Jean-Pierre Allegre, pg 58-64. Signaling System #7.

High Availability in the HP OpenCall SS7 Platform. Fault tolerance in computer systems is discussed and high availability is defined. The theory and operation of the active/standby HP OpenCall solution are presented. Switchover decision-making power is vested in a fault tolerance controller process on each machine, by Brian C. Wyld, Jean-Pierre Allegre, pg 65-71

A Benchtop Inductively Coupled Plasma Mass Spectrometer. The HP 4500 is the first benchtop ICP-MS. It has a new type of optics systems that results in a very low random background and high sensitivity, making analysis down to the subnanogram-per-liter (parts-per-trillion) level feasible. It can be equipped with HP’s ShieldTorch system, which reduces interference from polyatomic icons, by Yoko Kishi, pg 72-79

Audit History and Time-Slice Archiving in an Object DBMS for Laboratory Databases. Development of an object database management system allows rapid, convenient access to large historical data archives generated from complex databases, by Timothy P. Loomis, pg 80-89. ODBMS.

Glossary,  pg 80

Testing Policing in ATM Networks. Policing is one of the key mechanisms used in ATM (Asynchronous Transfer Mode) networks to avoid network congestion. The HP E4223A policing and traffic characterization test application has been developed to test policing implementations in ATM switches before the switches are deployed for commercial service, by Mohammad Makarechian, Nicholas J. Malcolm, pg 90-95

List of Acronyms, pg 90

MOSFET Scaling into the Future. 2D process and device simulators have been used to predict the performance of scaled MOSFETs spanning the 0.35-mm to 0.07-mm generations. Requirements for junction depth and channel doping are discussed. Constant-field scaling is assumed. MOSFET drive current remains nearly constant from one generation to the next and most of the performance improvement comes from the decreasing supply voltage. Gate delay decreases by 30% per generation, nearly the same trend as previous generations. However, this performance gain comes at the price of much higher off-state leakage because of the reduction of the threshold voltage. Various solutions to this high leakage are discussed., by Paul Vande Voorde, pg 96-100

Frequency Modulation of System Clocks for EMI Reduction. This paper focuses on clock dithering as an on-chip technique for EMI reduction. It is a survey paper based on information gathered from inside and outside HP’s Integrated Circuit Business Division (ICBD). It reviews the basic concept, the work that has been done at ICBD and elsewhere, ICBD customer experiences, and lessons drawn from these experiences about design, effectiveness, and customer implementation with ICBD, by Cornelis D. Hoekstra, pg 101-106. Electromagnetic Interference.

Fully Synthesizable Microprocessor Core via HDL Porting. Microprocessing integrated in superchips have traditionally been ported from third-party processor vendors via artwork. A new methodology uses hardware description language (HDL) instead of artwork. Having the HDL source allows the processor design to be optimized for HP’s process in much the same way as other top-down designers, by Jim J. Lin, pg 107-113

General-Purpose 3V CMOS Operational Amplifier with a New Constant-Transconductance Input Stage. Design trade-offs for a low-voltage two-stage amplifier in the HP CMOS14 process are presented and some of the issues of low-voltage analog design are discussed. The design of a new constant-transconductance input stage that has a rail-to-rail common-mode input range is described, along with the rail-to-rail class-AB output stage. The performance specifications and area of this amplifier are compared with a similar design in a previous process, CMOS34, by Derek L. Knee, Charles E. Moore, pg 114-120

Improving Heat Transfer from a Flip-Chip Package. The lid of an ASIC package can significantly increase the temperature of the die by impeding heat transfer. In flip-chip packages the backside of a die can be exposed by eliminating the lid, thus allowing a heat sink to be attached directly. Numerical finite difference methods and experimentation were used to investigate the differences between lidded and lidless flip-chip designs. The results demonstrate that a lidless package is a superior design because of the increased thermal conductivity between the die and the heat sink, by Cullen E. Bash, Richard L. Blanco, pg 121-125

Authors August 1997: Anne P. Scott, Kevin P. Burkhart, Ashok Kumar, Gregory [Greg] L. Ranson, Paul J. Dorweiler, Floyd E. Moore, D. Douglas [Doug] Josephson, Glenn T. Colon-Bonett [Bonet], Steven [Steve] T. Mangelsdorf, Raymond [Ray] P. Gratias, Richard M. Blumberg, Rohit Bhatia, John W. Blockhaus, C. Michael [Mike] Ramsey, Joseph [Joe] R. Bulter, David J. Ljung, James [Jim] C. Fong, Hoi-Kuen Chen, Martin D. Kruckenberg, Tarek Dehni, John M. O’Connell, Nicolas Raguideau, Denis Pierrott [Pierrot], Jean-Pierre Allegre, Brian C. Wyld, Yoko Kishi, Timothy [Tim] P. Loomis, Mohammad Makarechian, Nicholas J. Malcom, Paul Vande Voorde, Cornelis [Casey] D. Hoekstra, Jim J. Lin, Derek L. Knee, Charles E. Moore, Cullen E. Bash, Richard [Rich] L. Blanco, pg 126-131

Reader Forum: A letter from Dennis D. McCarthy and John A. Kusters regarding “The Global Positioning System and HP SmartClock”, page 60 in the December 1996 issue, pg 132

December 1997 v.48 n.5

Cover: An artistic rendition of global internet communications, showing fiber-optic technology as the backbone for universal connectivity

Tera Era, by Waguih Ishak, pg 2-3

Communications Challenges of the Digital Information Utility. The Internet and World Wide Web are forerunners of a digital information utility that in time will provide computing as well as information to society, just as other utilities provide water and electric power, by Joel S. Birnbaum, pg 6-10

[Author:] Joel S. Birnbaum, pg 6

Residential Communications. Establishing a communications infrastructure to get information to, from, or around a residence is not a straightforward task today. However, in the future the equipment and wiring within a residence for Internet communications will be treated the same as the wiring and equipment for services such as telephone, electricity, and cable television are treated today, by Daniel A. Pitt, pg 11-18

[Author:] Daniel [Dan] A. Pitt, pg 11

Optical Networks: Backbones for Universal Connectivity. Communications traffic in the world’s fiber-optic backbone network is growing more than 10% per year and the growth rate is accelerating. The ever-increasing bandwidth demands are being met by an array of technological innovations including higher time-division multiplex (TDM) transmission rates combined with wavelength-division multiplex (WDM) overlays, by Robert C. Bray, Douglas M. Baney, pg 19-31

[Authors:] Robert [Bob] C. Bray, Douglas [Doug] M. Baney, pg 19

Data Transmission for Higher-Speed IEEE 802 LANs Using Twisted-Pair Copper Cabling. Transmission at 424.8 Mbits/s using Category 5 cable can meet both industrial and the more stringent domestic emissions regulations. The design is robust in operation and the complexity is not much greater than that used for the 100-Mbit/s rate, by Eric Deliot, Alistair N. Coles, Steven G. Methley, pg 32-41

[Authors:] Steven [Steve] G. Methley, Alistair N. Coles, Eric Deliot, pg 41

SpectraLAN: A Low-Cost Multiwavelength Local Area Network. The first-generation SpectraLan module will allow existing 62.5-mm multimode fiber-optic links to carry four times higher data rates than is possible with conventional methods. Four-channel error-free operation at aggregate data rates of 2.5 and 4.0 Gbits/s has been demonstrated over distances of 500 m and 300 m, respectively. The module is compact and potentially low-cost, by Brian E. Lemoff, Lewis B. Aronson, Lisa A. Buckman, pg 42-52

[Authors:] Brian E. Lemoff, Lewis [Lew] B. Aronson, Lisa A. Buckman, pg 52

Gigabyte-per-Second Optical Interconnection Modules for Data Communications. A ten-channel parallel optical link module operating at 1 Gbit/s per channel has been developed in the POLO (Parallel Optical Link Organization) program. Key components include vertical-cavity surface emitting laser and detector arrays, bipolar transceiver ICs, a high-speed ball-grid array package, polymer waveguides, and multichannel ribbon fiber connectors. Applications of the POLO module include computer clusters, switching systems, and multimedia, by Kenneth H. Hahn, Kirk S. Giboney, Robert E. Wilson, Joseph Straznicky, pg 53-61

[Authors:] Kenneth [Ken] A. Hahn, Kirk S. Giboney, Joseph [Joe] Straznicky, Robert [Rob] E. Wilson, pg 61

Developing Leading-Edge Fiber-Optic Network Link Standards. Advances in fiber-optic network technology within Hewlett Packard are achieved by close cooperation between Hewlett-Packard Laboratories (HPL) and Hewlett-Packard’s Communications Semiconductor Solutions Division (CSSD). This paper explores the interaction between HPL and CSSD for the advancement of high-speed LAN standards, particularly in the ATM Forum and IEEE 802.3z (Gbit/s Ethernet). Details of major technical contributions to 622-Mbit/s ATM and Gbit/s Ethernet specifications are presented, by David G. Cunningham, Delon C. Hanson, Mark C. Nowell, C. Steven Joiner, pg 62-73

[Authors:] David G. Cunningham, Delon [Del] C. Hanson, Mark C. Nowell, C. Steven [Steve] Joiner, pg 73

1300-nm Strained Quantum Well Lasers For Fiber-Optic Communications. This paper describes new uncooled strained quantum well lasers for SONET/SDH systems. New Fabry-Perot lasers for short-haul and intermediate link applications are extremely reliable, have high ex-facet power, and have record low threshold currents, making lower packaging costs possible. Uncooled distributed feedback lasers for the long-haul market at 622 Mbits/s and 2.488 Gbits/s are discussed. These operate from – 40°C to +85°C with extremely good threshold and power characteristics, by William S. Ring, Simon J. Wrathall, Adrian J. Taylor, pg 74-85

[Authors:] William [Bill] S. Ring, Simon J. Wrathall, Adrian J. Taylog, pg 85

Modeled Optimization and Experimental Verification of a Low-Dispersion Source for Long-Haul 2.488-Gbit/s Systems. This paper describes microwave, laser, and fiber models that were used in the development of the HP LSC2500 2.488 Gbit/s laser diode module. Knowledge of the modeled behavior of the laser diode as a function of the input electrical pulse shape has led to deliberately shaping the input pulse to give the minimum wavelength excursion during direct modulation, and therefore a high yield of low-dispersion-penalty laser diodes. These devices can be successfully used for transmission distances in excess of 200 km, by Ian H. White, Joseph A. Barnard, Stephen M. Gee, Herbert Lage, Chris Park, Kevin A. Williams, Richard V. Penty, pg 86-100

[Authors:] Stephen [Steve] M. Gee, Kevin A.Williams, Joseph A. Barnard, Herbert Lage, Richard V. Penty, Chris Park, Ian H. White, pg 101

Flip-Chip Photodetector for High-Speed Communications Instrumentation. A family of 7-GHz bandwidth optical receivers and a nine-channel optical receiver with a gigabit-per-second data rate per channel have been developed for multigigabit lightwave test systems for long-haul fiber-optic telecommunications links and gigabit optical interconnects for computer systems. A new micro-flip-chip process, featuring liftoff-based small-diameter solder bumps, is incorporated with HP high-speed InP p-i-n photodetectors to minimize parasitic capacitance and inductance and enhance responsivity, by Susan R. Sloan, Tun S. Tan, David M. Braun, Tim L. Bagwell, Christopher P. Kocot, Joseph Straznicky, pg 102-109

[Authors:] Tun S. Tan, Christopher [Chris] P. Kocot, David M. Braun, Susan R. Sloan, Tim L. Bagwell, pg 110

A 2.488-Gbit/s Silicon Bipolar Clock and Data Recovery Circuit for SONET Fiber-Optic Communications Networks. Adjustment-free clock and data recovery for 2.488 Gbit/s SONET applications is provided by a 1.77W, 3.45 x 3.45-mm² chip implemented in a 25-GHz f_T silicon bipolar process. The chip has an on-chip VCO and operates from 2 to 3 Gbits/s over process, voltage, and temperature variations with a single off-chip filter capacitor. For network monitoring, a highly reliable loss-of-signal detector is provided. For good mechanical, thermal, and RF performance, a custom package was developed using HP’s fine-line hybrid process, by Richard Walker, Cheryl Stout, Chu-Sun Yen, Lewis R. Dove, pg 111-119

[Authors:] Richard [Rick] Walker, Cheryl Stout, Chu-Sun Yen, Lewis [Lew] R. Dove, pg 119

Testing Erbium-Doped Fiber Amplifiers. EDFAs can overcome losses in long fiber-optic links independent of the digital bit rate, and can amplify multiple signals in a wavelength-division multiplexed (WDM) systems architecture. As more and more EDFAs are deployed, designers add new features, creating a need for more sophisticated testing. This paper provides a brief survey of the tests required to characterize EDFAs, by James R. Stimple, pg 120-126

[Author:]  James [Jim] R. Stimple, pg 102

Hewlett-Packard Professional Books. Listed below are the books published in 1997, pg 127